Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STCLRL (64-bit)

Test 1: uops

Code:

  stclrl x0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.004

Integer unit issues: 1.004

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)0e0f1e223a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
730053285424627116111004156923292210206963010100420001000200011220169635492975732972327323153000100020002000400032724263011710011000100002000221003100004200332016443118352848139219722295339814447174748324531005166851479415292200010003274132822328093269932904
7300432968245210240010061606132717112075830031003200010002000109681683534929813331023264731230001000200020004000331992644117100110001000020002210021000362004222160341210928427396412452288039084448134842324411006164921485616420200010003276432778325683264132733
7300433162246190210010031589632705112057230031004200010002000110881689344929816325383264531330001000200020004000328062652117100110001000020002210021000052004320160051199818379396812502312139474443145440324311004174511557815128200010003268332819328253285532599
7300432704245220180011471576333272112126130041004200010002000109651689124929677327153270031030001000200020004000327452628117100110001000020000210031000062002222162511209708459398414542268140414443165955323561002164391466215378200010003325833312328543269733094
7300433142248250240010051595232786112076430051003200010002000109611687844930194327063279431430001000200020004000326982611117100110001000120002210021000022007202155511149408217387913492324939234440114655324231007171931551114728200010003325632822328053296032678
7300432790249150170010040585332712112071530041004200010002000110671690704930122326353303931030001000200020004000327522568117100110001000020002210031000032004222156061197918425410110462286440364442104349323071006166481496116322200010003299632821332573272933165
730043256824418021001003057343282511207383004100420001000200010974168853492969232635327163133000100020002000400032848263611710011000100002000221003100003200530216450118032836938948452301640254446124351323401003180101466716252200010003278532916328223272032734
730043319624522021001004060793309201207293003100420001000200010978168742492996932608327743103000100020002000400033269264311710011000100002000221006100006200262216340114433817938046422271639874440105053323701008164521484314831200010003287832820329463284232801
7300432824246170180010051606732722112071330031004200010002000109361688044929559327513323631230001000200020004000328632606117100110001000020002210031000162002322163461204118380406312482288239904442144443326921005163871478515258200010003309133318332083317232828
730043280824621017011006159503288111212043002100320001000200010973168673982979832734326953123000100020002000400033164259911710011000100002000221005100004200222216308121181840337099482328039314440125242323431004163661477414735200010003275032950328043275532800

Test 2: throughput

Code:

  stclrl x0, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0124

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40209701245252200200733128581640821207011279610127126578312540722207452000020100200002048293332344801124967042070064701226456836508540100203532000030200400007012468112020110099100100001010010000010020878111207571993010911102362705905801104211472208243910082013101161269912208156620000201007012770123701277012470128
4020470130525110000072310804176078116701097869128125577732540913207192000020100200002048684332364401694967044070086701226456236508140100202002000030200400007012467112020110099100100001010010000010020890212508231992710889102552675861361069210952210246710722013101161269912206426620000201007012770126701237012770126
4020470121525100000073291821179278144701117948128137568652540768206412000020100200002048604332317401064967047070085700916456536508240100202002000030200400007012567112020110099100100001010010000010020898212708411993110869102442713887481102210942236237312082013101161169911205736620000201007013170124701257012770126
402047012452510000007348184616967892701098049135129578862540745208462000020100200002048239332370302084967041070084701266456136508540100202002000030200400007012567112020110099100100001010010000010020913112927771992910865102552853897421078211242211140810561013101161269919206236620000201007012270129701007011970133
4020470133525222000073132820177681156701148188119131568192540779207912000020100200002047599332387501174967040070082701296456336508340100202002000030200400007012468112020110099100100001010010000010020882211038561992810871102332653931441220211352214241610562013101161169915207816620000201007012870124701257012670128
40204701275262220000712728481744891247010875814111134554122540731207622000020249200002048175332360301374967048070081701276456036508140100202002000030200400007012368112020110099100100001010010000010020882111707671992610906102522503913341036212932229245811042213101161169904208076620000201007012370126701237012570123
402047011852510000007352181017206513670110797712413256421254073620740200002010020000204745233226640121496704707008470128645593650834010020200200003020040000701226711202011009910010000101001000001002087711162776199311088910259253390938107221190223014049760113101161269910205836620000201007012970122701227012170127
40204701265262000000730727951712100152701088191111212157670254071820765200002010020000204813333227020127496704407008770124645653650814010020200200003020040000701226811202011009910010000101001000001002088221254786199351088110238294592538108721154221014289441013101161269912205916620000201007012470121701267012970126
402047012252520202007180280713528115270105814812212957156254084320720200002010020000204814533235770130496704207009070128645573650814010020200200003020040000701146711202011009910010000101001000001002095021138820199341094110252283390936111021132221224849762013101161169912206206620000201007012070124701247012870124
402047012152510000007331184917288515270111802913913156890254064620729200002010020000204838533223840994967041070085701306453436508640100202002000030200403127010068112020110099100100001010010000010020911111467801993110854102532953945341091210972222143010481113101161169911207886620000201007012770122701287012870128

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0129

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
400297012252610000007267180917841071007010979622138145561352540637206182000020010200002048447332326111454967046700857012364585365108400102002020000300204000070127701120021109101000010010100000102091001225786199391086210246280193542104121110518914591080101270116116991320610101020000200107012670131701277012670128
400247012752500000007231082717281051167011479628150135560732540616206432000020010200002047802332358802364967048700907012364593365111400102002020000300204000070133701120021109101000010010100000102094001186788199341087610229268193354104821118520513791080101270116126991920711101020000200107012970134701287013070131
40024701235250000000719508191688899670110788311501445626825406682080620210200102000020480773322853014149670517068970123645951865086400102002020303300204000070114681120021109101000010010100000102091601193770199331082510260292195356111221155517413791064101270216216991620590101020000200107012970129701287013070130
400247013352510000007368180315441051407011980018144138562952540552206062000020010200002048244332287411294967052700907012764595365105400102002020000300204000070133701120021109101000010010100000102091021170772199311085310255288193538138121101519114121008101270116226991620698101120000200107012970128701327013670132
400257012960600000007333078317281051487011379823140147566712540962206562000020010200002047444332286011114967048700887012564589365102400102002020000300204000070127691120021109101000010010100000102093401217769199341088010251299190588102921116516213821016101270116116991420704101020000200107013370132701307013070130
40024701325251010000725618501704113144701168282015315056399254067720713200002001020000204748733227411126496704570087701256458636510540010200202000030020400007013569112002110910100001001010000010209371122277919930109051025629319174211682104151891397952111270216116991720666101020000200107013470130701217012770136
400247012952600000007207082617281191127011385121157135562782540748206922000020010200002048261332231911744967048700917012564589365110400102002020000300204000070129691120021109101000010010100000102089401126772199301085210240280190140112421077519213841008111270316116991420731101020000200107012770129701307012770129
400247013352600000007286084517361071167011279538133142559332540828209812000020010200002047207332135901894967046700897012964589365103400102002020000300204000070128681120021109101000010010100000102090801203822199401089010203276190740106221118520614331008101270216326991320772101020000200107012670124701267013070128
40024701235251000000726618091728101144701117822812713656350254064820619200002001020000204729233224951132496704770086701306458336511040010200202000030020400007012669112002110910100001001010000010208692116176619932108511024327418634010732108851891406920101270116216992220627101020000200107012870133701277012670133
40024701275250000000730588818170494136706007892613614257030254062020647200002001020000204836333241700366496402870088701286458236510940010200202000030020400007013069112002110910100001001010000010209240124176319930108351024027418878899421080520014031016101270216236991520628101020000200107012970140701307012970130

Test 3: throughput

Code:

  stclrl x0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0133

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3020522018216491110000273181000022010207720235225503892662423412101002000083250041052286914674921706102201652201312154316216335301001974190410203200052020640009220131904111020110099100100001001000001002000003224269761000100171693695617256018300011171610193016002194271622764414002000010100220114220126220134220124220118
3020522012516490000000279150100022009411172022682550801273362274810100200008694956105249671451492170530220125220131215450621634530100179117291020320005202064000922012383011102011009910010000100100000100200000332427016100010017228370371711410320011171697760160021944417328060101002000010100220116220144220140220146220136
3020422011316480000000265050010022011610420249125503842684223186101002000084734571052500114494921702202201082201442154666216322301001936171210200200002020040000220108882111020110099100100001001000001002000003018269691003400166733721216811103100111722105542252221946415127703101002000010100220130220116220158220150220102
30204220135164900000002727900101220098204202325255085227633231731010020000841687010526182148449217059022014722011321544562163483010019142175102002000020200400002201258751110201100991001000010010000010020000033252674210000001681036802175391193200111716106020160021939419227651101002000010100220156220130220128220142220104
30204220107164900000002753310000220112105202196255074527220233961010020000844972010526767148449217043022013822010821542862162973010019002057102032000520206400092201399121110201100991001000010010000010020000031222737410000001659737064170621031001117169946016002194011462735913002000010100220120220137220121220126220093
302042201241649000000027228001012201300002017052550820277212313010100200008517613105251691488492170470220110220136215484621636530100179722681020320005202064000922012590611102011009910010000100100000100200000342727282100010016774370671707700320011171697060160021942119927233131002000010100220102220094220155220137220145
3020422015016490000000273350000022010808420186425504612788522588101002000085553511052622015564921704802201642201162154616216338301001817263810203200052020640009220172954111020110099100100001001000001002000003102774410000001746836817175121000011171611260016002193972002760710002000010100220126220148220132220138220140
30204220147164900000002691510000220102160202127255080027438231471010020000843900110527820156049217035022020322013121540562163613010016251621102032000520206400092201278821110201100991001000010010000010020057030027037100005017105370681694902131001117161058801600219407185271990002000010100220115220123220127220157220136
302052201351649000000027892000002201290129202126255055027472233551010020000822201210524891156249217049322012322010721546162163033010019112110102032000520206400092201059041110201100991001000010010000010020000000270021000100173953718217049020300011171710622016002194151772711601002000010100220116220134220138220128220124
302042201191649000010027779001002201160105202500255078028031226711010020000862279010525306153549217031022013322013921543762163133010017521904102032000520206400092201538161110201100991001000010010000010020000030212733710001501633236453169971153100111717107910160021939015826942131002000010100220114220122220130220106220092

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0257

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f223a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30025220172164910100316191612220252001720103525529713285520071100102000010681882105248440132649217115220226220236215415321645930010123125100202000020020400002202186681110021109633531010000101000001020028273442316411001602216384162421512150342520006401532731622219417332810902000010010220247220248220280220259220251
300242202721651101003147914002202378016201490255291132875200651001020000106285731052453901393492171492202262202322154133216512300101341261002020000200204021722022666711100211094787110100001010000010200252524423157110014002165341629215741528362610006401522921622219378032903092000010010220258220221220260220235220323
3002422030016501111031591150122022881718200956255295432940200961006020000106503551052463801354492172192202452202772154333216530300101371351002020000200204041322028972711100211095362010100001010000010200272731363152610016002154541497213911529342510006401532921622219406132770902000010010220323220267220279220276220295
300242202471650101003152815032202800180201792255293432745200981001020000105954891052642211393492172112202922202502154373216466300101411371002020000200204000022029266811100211095309010100001010000010200262604131576100160021650416062159115002520006401528221622219382232819992000010010220237220241220251220234220231
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