Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STADD (64-bit)

Test 1: uops

Code:

  stadd x0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.005

Integer unit issues: 1.005

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f191e1f22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6061696a6d6emap rewind (75)map stall (76)dispatch uop (78)79map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
7300534013255211111001004100531833881002194930061004200010002000109901692510104930922338563408431030000100020002000400033892264911710011000100012003320101210010014720035130201503610645179953574502415635364442134746328941002190281672217486200010003408534106340333404433973
730043404025501111000100210053913394300220113002100620001000200010991169797004930987337563400231030000100020002000400033979261711710011000100002003222100710011032001413221150411066907951361444240813577443374746329531004192531680517875200010003405734093340333406334074
730043409525501101000101010053643381101221023005100620001000200011001168266004930848338373404031030000100020002000400034031264011710011000100012003221100310013142003412020150491064907987356946241333568443354444329861005189671634217610200010003406134073340693405034118
7300434081255111110001029100533933878002210130051002200010002000109431685870049310013382934086310300001000200020004000340222658117100110001000020042001004100110520024132221499410735079523592452411735584439134354329541005189491674417709200010003420234042340623403434053
730043406725531110000100710053343395200220223005100420001000200010994168218004931005338463400531030000100020002000400034017266711710011000100002003232100710013042003212321147671057507987359144241563561443734648329641006191241686917632200010003403934077340303411633972
730043413225511111000100511053873390300219603006100520001000200010947168954004930966337963409431030000100020002000400034030268811710011000100002004222100610011252003410223149541062507982359147240743571444084243329881005191121673417776200010003407333928339973398134094
730043402825601110000100910052513388400220773006100520001000200010977168566004930965338043405131030000100020002000400033989266011710011000100002004220100610012242004412222150401096718041355242242293572443684142329011002192151663717749200010003404634021340443404234044
730043407025511111010100210053313389400220233003100320001000200010924168295004930985338773408531030000100020002000400033965264811710011000100002003200100410013152003513021148261053407999361146240503498443985448328971001190131691617655200010003411434034340433391434016
730043403825501111000100510053103392800220773005100520001000200010932169041004931043338313401031030000100020002000400033947266211710011000100002004222100610010152002510021149091068407962356439241393614443464349330491004192181684217613200010003405834047340553404934138
7300434077255011101001005110527633860002200330031005200010002000109901696430049309853388334102310300001000200020004000338922641117100110001000020042201005100181112001312321150731059907963360341241963521443894449329791003188691685817475200010003402434116340653405534084

Test 2: throughput

Code:

  stadd x0, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0071

retire uop (01)cycle (02)03mmu table walk instruction (07)0f1e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
402093007122510578108531728116148300567732821122713153254124121174200002010020000916652141262813114926991300713007124818032502940100202002000030200400003007169112020110099100100001010010000110020926115510860110311032127819313412332118919330063410841310216223006821229101020000201003007230072300723007230072
402043007122500563508361712110156300567982719124513169254125721202200002010020000916950141270613794926991300683007124818032502940100202002000030200400003007168112020110099100100001010010000110020908138310190109261030624618973611402131618335077310621310216223006821200101020000201003007230072300723007230072
402043007122600573408301688116152300568082423818613236254122321228201052010020000916846141264113224926991300713007124815032502940100202002000030200400003007169112020110099100100001010010000110020896130611050109111030924919155412892123623344073210861310217223006821101101020000201003007230072300723007230072
402043007122500589808471704109200300567932421923113168254121921170200002010020000916596141265113484926991300713007124815032502940100202002000030200400003007169112020110099100100001010010000110020879124710670109961031327518814412512120725384077610421310217223006821200101020000201003007230072300723007430072
402043007122500577218261704109164300568033624619513202254125021272200002010020000917107141265613044926991300713007124817032502940100202002000030200400003007169112020110099100100001010010000110020906118910520109261030228219053212392125223380073610291310216223006821153101020000201003007230082300723007230072
402043007122500576018421696101152300567873321719413197254123021317200002010020000916733141255713104926991300713007124818032502840100202002000030200400003007170112020110099100100001010010000110020896119411160109581032228919213212412123324344062810921310216223006821222101020000201003007230072300723007230072
402043007122500578307881728114164300567782321419913219254111921170200002010020000916933141251413404926991300713007124815032502840100202002000030200400003007168112020110099100100001010010000110020894118510540109261031229218793212792130320345074610961310216223006821001101020000201003007230072300823007230210
402043007122500571608231696107220300567772722123113201254124421247200002010020000916981141254213194926991300713007124815032502940100202002000030200400003007169112020110099100100001010010000110020908127610420109491031925419393411992122224324080910641310216223006821129101020000201003007230072300723007230072
402043007122500564208371744115144300567903023524813266254129221233200002010020000916900141253813354926991300713007124813032502940100202002000030200400003007168112020110099100100001010010000110020946124010570109511029727619314011952130721360169210521310217223006821124101020000201003007230072300723007230072
40204300712250058170832173611011230056799352152361317325412972117620000201002000091679314127091347492699130068300712481403250294010020200200003020040000300717011202011009910010000101001000011002091012749750109561033129219213212642128820364069710661310216223006821119101020000201003007230072300723007230072

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0071

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4002930071225100101015886782610080011612030056768100230240132332541124212742000020010200009250151427071033849269913007130071248370325052400102002020000300204000030071681120021109010100001001010000110209171312999840110621035429048965030432147719402070410450012702161130068211949920000200103007230072300723007230072
40024300712251011000059307823100744114923005677711220726513166254115021153200002001020000916843141267503544926991300713007124839032505140010200202000030020400003007169112002110901010000100101000011020925141236102201094310346248089740130321365214508731105913112701161130068211319920000200103008230072300723007230072
40024300712251000000060287819100680112152300568071182441901315225411662119220000200102000091576714130850324492699130071300712483703250524001020020200003002040000300716811200211090101000010010100001102090415118295101098810331278087552143921344164908607101113312701161130068210929920000200103007230072300723007230072
4002430071225202200005925118041007441051203005681310124324613210254123421183200002001020000915865141261813404926991300683007124838032505140010200202000030020400003007167112002110901010000100101000011020902211127946010946103652753912381282213041741510668118017012701161130068211289920000200103007230072300723007230072
400243007122520020000588911806100696112112300567939621829513204254123521123200002001020000916444141259113674926991300713007124837032505140010200202000030020400003007168112002110901010000100101000021020891171120890011002103392723900381340213251650312611100417012701161130068212349920000200103007330072300723007230072
40024300712262002000059641279710072010914030056755126231256132252541220212302000020010200009161481412724033649270013007130071248390325051400102002020000300204000030071691120021109010100001001010000110209081611401039010960103322640881341334213272138910619101617012701161130068211569920000200103007230072300743007230072
40024300712252000000060411077510069611510830056799135226260131732541224210992000020010200009152341412657033649269913006830071248400325051400102002020000300204000030071681120021109010100001001010000110209331711271070010993103132883922541353213431344010657102417012701161130068210849920000200103007230072300723007230072
40024300712252000000060581378210072010614030056757111220259131922541221212282000020010200009166141412516133149269913006830071248370325052400102002020000300204000030071691120021109010100001001010000110209232111921080011038103552727891381215213552242412639104517012701161130068211169920000200103007230072300723007230072
400243007122520200000593614788100720104144300567739720625613187254122321127200002001020000916125141269703244926991300713007124840032505240010200202000030020400003007167112002110901010000100101000021020901161186110001100310348284388036124121307234101063094017012701161130068211129920000200103007230072300723007230072
4002430071225202200005841138051007121121403018086713819122713218254126021170200002001020000915889141264303154926991300683007124854032505140010200202000030020400003007169112002110901010000100101000011020911171211979010961103372673871341272213021843111683105516012701161130068210849920000200103007230072300723007230191

Test 3: throughput

Code:

  stadd x0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.2991

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30206108353796000010016866110010452708885832254005919613200961010020000456165748994350135491010380103706103488993656984583010067976910203200052020640009103207605111020110099010010000100100001100200000353220942100010095092924210452103101117172401600101852211905814102000010100102957102088102276102327103846
30204102991789000000019737100198853000828832541882211212048910100200004349961487000301964910116701037191029449843369804430100112097710203200052020640009103168445111020110099210010000100100000100200000001993110000001058130129999413135011171823016001059551204340102000010100100139994889984610044498589
302049619771300000001667210001023211100838742541842201212013410100200004363987477621401314910193101044911043649855071015083010074565410203200052020640009104594449111020110099010010000100100001100200000313121400100010098812886110249128350111717202160010100125198670132000010100101650102116101796101666105593
3020410537879600000001887100011032631119836702540710210832048110100200004425874481695001594999575010330510322998816699022301007016631020320005202064000910426956211102011009901001000010010000010020000034019606100010099722990911436126340111717190160010439316194851402000010100104934105515104742104601104305
30204976577500000000189000001100497199828952541301217302052310100200004633902496946902354999220010107410226898094798924301008756991020320005202064000910483050011102011009901001000010010000010020000034312029410001009141292149689024310111716100160010312111198451402000010100104429104509103395103515105100
302041044277800000000204801010106033081283707254024619610204141010020000470205349929890168499923701044471027749782879919530100835590102032000520206400099694151111102011009901001000010010000010020000034019558100010011066302521002912835011171724016009998935188520102000010100102859102083102406103013102453
302041013297650000000197361001102638101181984253937818828200101010020000454315649056080356491001820102240103025980836983383010011931177102032000520206400091029773661110201100990100100001001000001002000003134206471000100116093173089071270011171628016001031006189311010200001010098915972709910899394102147
3020410492479400000002006400119951219086103254227320960201641010020000472254149939670247499711301009301020139784269848430100827101610203200052020640009103138471111020110099010010000100100001100201560030210231004482412352293181016612500111717210160010315813205151402000010100104858105848105561103873102093
30204103510785000000019217000010094724479856254013618995207391010020000381064645288770123499764809888798985924707949203010088894210412200052020640009104021366111020110099010010000100100001100200000353120767100001010303291411057313031011171600160010451715194751313200001010010269110245110284010194996727
302041001307530000000216721011104358001281901253935018823209341010020000425924848209910834999348010486810502197801797026301001160878102032000520206400091042885381110201100990100100001001000001002000003125188511000100857129028104990303101117180016001039836209231314200001010099457100336102470103457105386

1000 unrolls and 10 iterations

Result (median cycles for code): 11.1706

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
300261111248321000000024964110011171601212916922544989249652006910010200005467277533230509364910881001117671118681073253107664300103134100202000020020400001115184491110021109287311010000101000001020025031360259351000100147353430815381153134251006685652774511291343340010102000010010114338114292113715114348112459
30024114279858001111262524142110011188611213912632546010250942007810010200005489855533497009154910867901117771114681072533108087300103115100202000020020400001118354121110021109241731010000101000001020000031360234161000100142143512512492129310000640302152211150612610710102000010010111420111543111543111460111376
300241116438350111000025089141021117929171691249254339123928200061001020000551244553148581993491084290111358111520107127310791030010332710020200002002040000111872445111002110927280101000010100000102002727295402347310017001412035007153451631372530064002162211142002476910102000010010112054111871111755111824111641
3002411148783900000000242701100111412918189156425444422494320009100102000054596725316941011684910870201117791117421073953107856300101622100202000020020400001117704941110021109269191010000101000001020027273654021050100170111075320111239110310000640232162211144812289714102000010010111573111583111574111638111558
30024111605835000000002443210001116709180915952543819229482001810010200005460471531590301155491085930111581111592107318310801530010142310020200002002040000111511512111002110927065101000010100000102002827053023607100150214592336651503115303626100640312152211113462412313132000010010111847111527111706111887111679
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