Firestorm: LDRSB (register, uxtw, 64-bit) measurements

Code:

  ldrsb x0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	61	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	2	1	45	1	0	1	379	2	12	12	0	25	1000	1000	1000	15037	1	0	397	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	0	73	0	1	16	2	2	391	10	10	4	1000	395	395	397	395	395
1004	394	2	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15018	0	0	374	394	217	3	232	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	1	39	1039	6	1	39	43	0	73	9	1	16	1	1	391	10	10	0	1000	375	395	376	399	395
1004	394	3	1	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15208	0	0	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	0	0	43	0	73	0	1	16	1	1	391	0	0	4	1000	395	375	395	395	395
1004	394	3	1	45	1	0	1	383	2	12	12	16	25	1000	1000	1000	15018	0	0	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1000	6	1	39	43	0	73	0	1	16	1	1	391	10	0	4	1000	395	395	395	395	395
1004	394	3	1	45	1	0	0	359	2	0	12	0	25	1000	1000	1000	14060	0	0	394	394	218	3	232	1000	1000	2000	394	56	1	1	1001	1000	1000	1000	43	1039	0	0	1039	6	0	39	43	0	73	0	1	16	1	1	391	10	10	4	1000	395	395	375	395	397
1004	394	3	1	0	0	0	1	379	2	12	12	16	25	1000	1000	1000	15037	1	9	374	394	217	3	232	1000	1000	2000	374	77	1	1	1001	1000	1000	1000	43	1039	0	42	1039	6	1	39	43	0	73	9	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	1	45	1	0	1	379	0	12	12	16	25	1000	1000	1000	14060	0	0	394	394	217	3	232	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1000	0	42	1039	6	0	39	43	2	73	9	1	16	1	1	391	10	10	4	1000	395	395	395	395	375
1004	394	2	1	45	0	0	1	379	2	0	12	16	25	1000	1000	1000	15037	1	9	394	394	217	3	252	1000	1000	2000	374	57	1	1	1001	1000	1000	1000	0	1039	0	39	1039	6	1	39	0	0	73	0	1	16	1	1	391	10	10	4	1000	395	395	395	395	375
1004	394	3	1	45	1	0	1	379	2	12	12	0	25	1000	1000	1000	14989	0	0	394	394	217	3	252	1000	1000	2000	374	77	1	1	1001	1000	1000	1000	43	1039	0	0	1000	6	0	39	43	0	73	0	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	45	0	1	1	380	2	12	12	16	25	1000	1000	1000	14060	1	9	394	374	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	43	1039	6	1	0	0	0	73	0	1	16	1	1	391	10	10	4	1000	395	395	375	375	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70055	525	0	0	1	0	1	1	2	1	70046	1	1	69792	59708	25	40112	30109	10003	30100	10000	616104	3342158	49	66981	70061	70061	64657	3	65064	40100	30200	10000	60200	20000	70043	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69818	30003	6	0	6	10000	30100	70044	70056	70044	70056	70056
40204	70055	525	0	0	0	0	0	1	2	1	70046	1	1	69792	59712	25	40112	30109	10003	30100	10000	616104	3342734	49	66981	70061	70061	64657	3	65011	40100	30200	10000	60200	20000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	1	10001	0	1	1	0	0	2610	1	71	1	1	69824	30006	0	6	6	10000	30100	70050	70062	70062	70062	70062
40204	70061	524	1	0	1	0	0	0	3	0	70034	1	0	69792	59708	25	40112	30109	10003	30100	10000	616104	3342734	49	66981	70049	70049	64657	3	65041	40100	30200	10000	60200	20000	70043	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69824	30009	0	6	6	10000	30100	70062	70050	70062	70062	70062
40204	70061	525	1	1	0	1	0	0	3	1	70040	1	1	69786	59714	25	40108	30106	10001	30100	10000	615971	3342446	49	66963	70055	70055	64651	3	65056	40100	30200	10000	60200	20000	70049	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	2	10002	0	0	2	10001	1	2	1	1	0	2610	1	71	1	1	69818	30006	6	6	6	10000	30100	70099	70125	70059	70056	70044
40204	70043	524	0	0	0	0	0	0	7	0	70046	1	1	69780	59720	25	40112	30109	10008	30100	10000	616104	3342734	49	66969	70049	70061	64645	3	65009	40100	30200	10000	60200	20000	70055	77	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69824	30009	6	6	6	10000	30100	70062	70062	70062	70062	70050
40204	70061	525	1	1	1	0	0	0	3	1	70040	1	1	69710	59714	25	40104	30106	10002	30100	10000	616050	3342446	49	66975	70055	70055	64651	3	65029	40100	30200	10000	60200	20000	70043	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69806	30006	6	6	6	10000	30100	70056	70124	70111	70054	70056
40204	70055	524	0	0	0	0	0	0	2	1	70040	1	1	69786	59714	25	40108	30106	10002	30100	10000	615971	3341867	49	66975	70055	70043	64651	3	65052	40100	30200	10000	60200	20000	70061	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	2	10002	0	0	2	10001	1	2	0	1	0	2610	1	71	1	1	69818	30003	0	6	6	10000	30100	70044	70056	70056	70044	70056
40204	70043	525	0	0	0	0	0	0	2	1	70046	1	0	69780	59720	25	40112	30109	10003	30100	10000	615996	3342734	49	66981	70061	70061	64657	3	64978	40100	30200	10000	60200	20000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69824	30009	6	6	0	10000	30100	70062	70062	70050	70050	70050
40204	70049	525	1	0	1	1	0	0	2	1	70040	1	1	69786	59714	25	40108	30103	10001	30100	10000	616050	3342446	49	66975	70055	70055	64651	3	65044	40100	30200	10000	60200	20000	70061	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	2	10004	1	2	2	10001	1	2	1	1	1	2610	1	71	1	1	69818	30003	6	6	0	10000	30100	70044	70056	70056	70044	70044
40204	70055	525	0	0	0	0	0	0	1	0	70046	1	1	69792	59720	25	40112	30106	10003	30100	10000	616104	3342734	49	66981	70049	70061	64657	3	64958	40100	30200	10000	60200	20000	70043	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	2	10001	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69824	30006	0	6	6	10000	30100	70062	70050	70050	70062	70062

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	1e	1f	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	0	0	1	0	0	0	70020	69744	59713	25	40014	30013	10002	30010	10000	617068	3341470	0	49	66955	70047	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	0	2520	3	71	3	5	69810	30003	6	0	0	10000	30010	70046	70416	70053	70049	70036
40024	70035	524	0	0	0	0	1	0	0	0	70032	69730	59706	25	40014	30013	10001	30010	10000	617068	3342062	1	49	66967	70047	70047	64653	3	64960	40010	30020	10000	60408	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	1	0	2520	3	71	5	5	69798	30003	6	6	6	10000	30010	70071	70038	70055	70048	70048
40024	70047	524	0	0	0	0	1	0	1	0	70032	69729	59706	25	40014	30010	10001	30010	10000	617068	3341470	0	49	66955	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	1	0	2520	5	71	5	4	69798	30000	0	6	6	10000	30010	70079	70050	70056	70036	70048
40024	70035	525	0	0	0	0	1	0	1	0	70032	69733	59695	25	40014	30013	10001	30010	10000	616952	3342350	1	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	0	1	0	2520	2	71	3	3	69810	30000	0	6	6	10000	30010	70056	70048	70048	70048	70036
40024	70047	524	0	0	0	0	0	0	1	0	70032	69736	59706	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66955	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	2	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	0	1	0	2520	4	71	5	3	69798	30003	0	0	6	10000	30010	70055	70053	70070	70048	70041
40024	70047	525	0	0	0	0	0	0	1	0	70032	69732	59706	25	40014	30013	10000	30010	10000	617068	3342062	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	0	2520	2	71	4	4	69810	30003	6	0	6	10000	30010	70052	70398	70051	70078	70048
40024	70047	525	0	0	0	0	1	0	1	0	70032	69743	59695	25	40010	30010	10001	30010	10000	616952	3341470	1	49	66967	70057	70050	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	0	2520	3	71	3	3	69810	30000	6	6	6	10000	30010	70105	70040	70048	70048	70036
40024	70047	524	0	0	0	0	1	0	0	0	70020	69729	59695	25	40010	30013	10001	30010	10000	616952	3342062	0	49	66967	70049	70053	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	2	2520	3	71	4	6	69810	30000	6	6	6	10000	30010	70102	70051	70053	70048	70036
40024	70047	524	0	0	0	0	6	0	1	0	70020	69730	59706	25	40010	30010	10001	30010	10000	617068	3341470	1	49	66967	70047	70035	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	3	10000	1	0	0	2520	3	71	3	3	69798	30003	6	6	6	10000	30010	70088	70052	70052	70036	70048
40024	70047	525	0	0	0	0	0	0	0	0	70032	69731	59709	25	40014	30010	10001	30010	10000	617068	3341470	1	49	66967	70035	70047	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	0	0	0	2520	4	71	4	5	69810	30003	6	6	6	10000	30010	70105	70049	70051	70036	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	0	0	0	0	0	1	0	0	1	70042	69788	59717	25	40104	30106	10005	30262	10000	616014	3342254	49	66977	0	70041	70057	64653	0	3	64955	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70042	70058	70058	70058
40204	70057	524	1	1	1	0	0	2	0	1	0	70036	69782	59710	25	40104	30103	10000	30100	10000	616014	3342254	49	66974	0	70035	70035	64647	0	3	65041	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10003	64	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69823	30006	10	10	10	10000	30100	70042	70058	70058	70058	70058
40204	70057	525	1	0	1	0	0	2	0	1	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	0	3	65038	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	1	10001	0	1	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69820	30003	10	10	10	10000	30100	70058	70042	70058	70042	70058
40204	70057	525	1	1	0	0	0	2	0	0	0	70036	69788	59716	25	40108	30103	10001	30100	10000	616078	3342542	49	66977	0	70057	70057	64653	0	3	65034	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10006	2	0	10001	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	0	10	10000	30100	70058	70058	70058	70058	70058
40204	70041	525	1	0	0	0	0	1	0	1	1	70026	69791	59701	25	40108	30103	10002	30100	10000	616078	3342542	49	66961	0	70060	70057	64656	0	3	65020	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10001	0	0	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	10	0	10000	30100	70042	70058	70058	70058	70058
40204	70057	525	1	1	0	0	0	2	0	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616078	3342542	49	66977	0	70041	70057	64637	0	3	65051	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70042	70058	70058	70058	70058
40204	70057	525	1	0	0	0	0	2	0	1	0	70026	69788	59716	25	40104	30106	10001	30100	10000	616068	3342542	49	66961	0	70057	70057	64653	0	3	65033	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10003	0	2	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69804	30003	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70042	525	1	1	0	0	0	2	0	1	1	70026	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70057	64637	0	3	65046	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	0	2	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30003	10	0	0	10000	30100	70042	70058	70058	70058	70042
40204	70041	525	1	1	0	0	1	2	0	1	0	70045	69791	59719	25	40108	30106	10002	30100	10000	616078	3341769	49	66971	0	70051	70051	64631	0	3	65051	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10002	0	1	1	10000	0	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70042	70058	70058	70061	70042
40204	70057	524	1	1	1	0	0	1	0	1	0	70042	69791	59716	25	40108	30106	10002	30100	10000	616068	3341769	49	66961	0	70041	70041	64637	0	3	65043	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	0	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69817	30006	10	0	10	10000	30100	70058	70058	70058	70058	70058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	0	0	0	0	0	0	0	0	1	0	1	0	0	0	70036	69778	59710	25	40014	30013	10002	30010	10000	616991	3342254	1	49	66971	0	70051	70051	64653	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	5	71	5	4	69798	30003	10	10	10	10000	30010	70036	70036	70052	70052	70052
40024	70035	524	0	0	0	0	0	0	0	0	1	0	1	0	0	0	70036	69775	59695	25	40010	30013	10001	30010	10000	616991	3342254	1	49	66955	0	70035	70041	64675	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	0	2520	4	71	4	2	69798	30003	10	10	0	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	1	0	0	1	1	0	0	1	0	0	0	0	0	70036	69775	59695	25	40010	30010	10001	30010	10000	616991	3342254	0	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	0	2520	2	71	4	5	69798	30003	10	0	10	10000	30010	70051	70055	70052	70052	70036
40024	70051	525	0	0	0	0	1	0	0	0	0	0	0	0	0	0	70036	69775	59716	25	40018	30013	10000	30010	10000	617068	3341614	1	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	1	10000	0	2	4	10003	0	0	1	0	2	0	2520	4	71	2	4	69991	30014	0	10	10	10000	30010	70150	70052	70244	70052	70058
40024	70035	525	0	0	0	0	0	0	0	0	0	0	1	0	0	0	70036	69775	59710	25	40018	30016	10000	30010	10000	616991	3342254	1	49	66974	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	3	10000	1	1	1	0	0	0	2520	4	71	4	2	69814	30003	0	0	10	10000	30010	70043	70058	70058	70052	70052
40024	70054	525	0	0	0	0	0	0	0	0	1	0	0	0	0	0	70036	69775	59710	50	40014	30010	10000	30010	10000	617045	3342302	1	49	66955	0	70051	70051	64669	3	64960	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	5	71	4	4	69798	30003	10	10	10	10000	30010	70052	70052	70052	70036	70052
40024	70051	524	0	0	0	0	0	0	0	0	0	0	1	0	0	0	70036	69775	59695	25	40010	30010	10001	30010	10000	616991	3341470	1	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	2520	3	71	4	3	69798	30003	10	10	0	10000	30010	70058	70042	70058	70052	70052
40024	70051	524	0	0	0	0	0	0	0	0	0	0	1	0	0	0	70036	69781	59695	25	40010	30013	10001	30010	10000	617045	3342542	0	49	66961	0	70051	70035	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	2520	4	71	4	5	69814	30000	0	0	10	10000	30010	70056	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	0	0	0	0	0	0	0	0	70036	69775	59710	25	40010	30013	10000	30010	10000	617068	3342254	0	49	66971	0	70035	70051	64653	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	1	2520	5	71	4	4	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70121	524	0	0	0	0	0	0	0	0	1	0	0	0	0	0	70020	69775	59716	25	40010	30013	10000	30010	10000	617068	3342254	1	49	66971	0	70051	70035	64653	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	1	10001	0	0	1	10000	0	1	1	0	0	0	2520	2	71	4	4	69814	30003	10	0	10	10000	30010	70052	70036	70036	70052	70052

Test 4: throughput

Count: 8

Code:

  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]
  ldrsb x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26722	200	1	0	0	386	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80014	500	1167875	0	49	23627	26722	26722	16650	6	16743	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	80035	0	35	80000	6	1	0	39	1	1	1	5118	0	16	0	26704	6	0	2	80000	100	26723	26723	26708	26708	26708
80204	26722	200	0	0	0	416	0	0	1	26710	2	0	18	0	25	80100	100	80000	100	80015	500	1167875	0	49	23627	26722	26707	16650	6	16674	80115	200	80024	200	160048	26731	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80000	0	0	80035	6	1	35	39	1	1	1	5118	0	16	0	26704	0	6	2	80000	100	26723	26723	26708	26723	26723
80204	26707	201	0	0	0	338	0	0	0	26707	2	0	18	12	25	80100	100	80000	100	80014	500	1167875	0	49	23642	26722	26722	16635	6	16680	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80035	0	35	80000	0	0	0	0	1	1	1	5118	0	16	0	26719	6	6	0	80000	100	26723	26723	26723	26723	26708
80204	26722	200	0	0	0	393	1	0	1	26707	2	0	0	11	25	80100	100	80000	100	80014	500	1159814	0	49	23642	26707	26707	16650	6	16685	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80035	0	0	80035	6	1	0	0	1	1	1	5118	0	16	0	26704	6	6	2	80000	100	26723	26708	26723	26723	26708
80204	26722	200	0	0	0	395	0	0	1	26707	0	0	0	0	25	80100	100	80000	100	80014	500	1166596	0	49	23642	26707	26722	16650	6	16680	80114	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	35	80000	0	1	0	43	1	1	1	5118	0	16	0	26719	0	6	2	80000	100	26723	26723	26708	26723	26708
80204	26707	200	0	1	0	21	0	0	1	26707	2	18	18	12	25	80100	100	80000	100	80014	500	1167875	0	49	23642	26722	26727	16655	6	16747	80114	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	0	80000	6	1	35	0	1	1	1	5118	0	16	0	26719	6	6	2	80000	100	26708	26708	26723	26723	26708
80204	26707	200	0	0	0	362	0	0	0	26707	2	0	18	12	25	80100	100	80000	100	80015	500	1166596	1	49	23642	26722	26722	16650	6	16674	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	35	80000	6	1	0	39	1	1	1	5118	0	16	3	26719	6	6	2	80000	100	26723	26723	26723	26723	26708
80204	26707	200	0	0	0	386	1	0	1	26707	2	18	0	12	25	80100	100	80000	100	80015	500	1166596	0	49	23642	26707	26722	16650	6	16813	80114	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80000	0	35	80035	0	0	0	39	1	1	1	5118	0	16	0	26719	6	6	2	80000	100	26708	26723	26723	26723	26723
80204	26707	200	0	0	1	3	1	0	1	26707	2	18	0	12	35	80100	100	80000	100	80014	500	1166596	0	49	23642	26707	26711	16635	6	16738	80115	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80035	0	0	80035	6	0	35	0	1	1	1	5118	0	16	0	26719	0	6	2	80000	100	26708	26723	26723	26723	26728
80204	26722	200	0	1	0	45	0	0	1	26707	2	0	0	12	25	80100	100	80000	100	80014	500	1167875	0	49	23627	26707	26722	16650	6	16700	80115	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	0	80035	6	0	0	39	1	1	1	5118	0	16	0	26719	6	6	2	80000	100	26723	26708	26708	26723	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26741	201	1	1	0	0	0	0	0	0	67	0	3	26700	3	0	7	21	25	80010	10	80260	10	80000	50	1168286	1	49	23660	26763	26736	17051	3	16716	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	21	43	0	80019	0	0	0	64	80000	6	1	59	43	19	1	5020	4	16	0	2	2	26738	13	0	5	80000	10	26750	26717	26738	26715	26716
80024	26737	200	1	1	1	0	0	0	0	0	21	0	2	26700	2	7	7	19	25	80010	10	80000	10	80000	50	1166960	1	49	23657	26715	26737	16681	3	16716	80010	20	80000	20	160000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	21	43	0	80058	0	0	0	61	80040	6	1	58	43	19	0	5020	2	16	0	3	3	26733	13	13	5	80000	10	26754	26846	26716	26737	26738
80024	26736	200	1	1	1	1	0	0	0	0	67	1	0	26737	2	7	7	0	25	80010	10	80000	10	80000	50	1164225	0	49	23656	26736	26736	16682	3	16695	80010	20	80000	20	160000	26714	85	1	1	80021	10	9	1	10	80000	10	80000	1	10	80019	19	44	0	80058	0	0	0	61	80000	6	1	58	43	19	1	5020	2	16	0	2	2	26712	13	0	5	80000	10	26715	26737	26737	26737	26741
80024	26715	200	1	0	1	1	1	0	0	0	66	0	2	26726	3	0	0	1	25	80010	10	80000	10	80000	50	1172009	0	49	23657	26736	26737	16660	3	16716	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80019	0	1	0	61	80040	6	1	59	43	19	1	5020	2	16	0	2	2	26711	0	13	5	80000	10	26741	26719	26738	26738	26737
80024	26738	200	1	0	0	1	0	0	0	0	67	0	3	26700	3	7	7	20	25	80010	10	80000	10	80000	50	1167219	0	49	23657	26736	26739	16660	3	16717	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	21	0	0	80579	1	2	0	60	80000	0	1	59	43	19	1	5020	2	25	0	2	2	26733	13	13	5	80000	10	26749	26737	26737	26737	26715
80024	26737	200	1	0	1	1	0	0	0	0	67	0	2	26734	3	7	0	20	25	80010	10	80000	10	80000	50	1166722	1	49	23660	26740	27035	16688	3	16695	80010	20	80000	20	160000	26714	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	0	0	80059	1	1	2	64	80039	0	1	19	43	19	1	5020	2	16	0	2	2	26712	13	0	5	80000	10	26738	26737	26738	26737	26737
80024	26736	201	1	1	1	1	0	0	0	4	67	0	0	26699	0	7	7	19	25	80010	10	80000	10	80000	50	1165304	1	49	23665	26737	26714	16681	3	16716	80010	20	80000	20	160000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80020	20	43	0	80059	1	0	1	60	80041	0	0	58	0	19	1	5020	2	16	0	2	2	26715	13	13	0	80000	10	26748	26748	26741	26737	26738
80024	26740	200	1	0	1	2	0	0	0	0	21	0	3	26704	2	0	7	0	25	80010	10	80000	10	80000	50	1167219	1	49	23657	26736	26715	16681	3	16734	80544	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	43	0	80059	1	0	0	61	80000	6	0	59	0	19	2	5020	2	16	0	2	2	26734	13	13	5	80000	10	26750	26738	26716	26738	26737
80024	26714	201	1	0	0	0	0	0	0	0	79	1	2	26725	2	7	7	1	25	80010	10	80000	10	80000	50	1167736	0	49	23656	26715	26737	16681	3	16716	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	44	0	80058	0	0	1	60	80041	6	0	58	43	19	0	5020	2	16	0	2	2	26712	0	13	5	80000	10	26741	26737	26741	26829	26738
80024	26737	200	1	1	1	1	0	1	0	0	76	0	3	26720	3	7	7	33	25	80010	10	80000	10	80000	50	1165304	0	49	23657	26736	26736	16681	3	16716	80010	20	80000	20	160000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80020	20	0	0	80019	0	0	0	61	80039	6	1	58	43	19	1	5020	2	16	0	2	2	26733	13	13	5	80000	10	26749	26715	26737	26737	26737

LDRSB (register, uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations