Firestorm: LDR (register, uxtw, 64-bit) measurements

Code:

  ldr x0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	381	2	1	1	45	0	0	3	379	2	12	12	16	25	1000	1000	1000	15044	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	7	48	1039	6	1	39	43	77	4	16	4	4	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	45	0	0	3	379	2	12	12	16	25	1000	1000	1000	14989	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	77	4	16	4	4	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	3	379	2	12	9	20	25	1000	1000	1000	14989	397	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	45	1039	6	1	39	43	77	4	16	4	4	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	3	381	2	12	12	16	25	1000	1000	1000	15018	394	394	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	77	4	16	4	4	391	10	10	4	1000	395	395	396	395	395
1004	394	2	0	0	45	0	0	3	379	2	0	7	16	25	1000	1000	1000	15018	394	394	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	77	4	16	4	4	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	3	379	2	12	7	16	25	1000	1000	1000	15018	394	394	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	77	4	16	4	4	395	14	10	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	3	383	2	12	7	19	25	1000	1000	1000	15274	394	398	221	3	252	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	38	44	77	4	16	4	4	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	3	383	2	1	7	19	25	1000	1000	1000	15365	394	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	0	1038	6	1	38	44	77	4	16	4	4	396	14	14	7	1000	399	408	399	399	395
1004	398	3	0	0	44	0	0	3	383	2	1	9	19	25	1000	1000	1000	15274	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1039	0	38	1038	6	1	38	44	77	4	16	4	4	395	14	14	7	1000	399	395	399	399	399
1004	403	3	0	0	44	0	0	3	383	2	1	7	19	25	1000	1000	1000	15208	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	77	4	16	4	4	395	10	14	7	1000	399	395	395	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70056	525	1	0	0	1	1	1	0	0	0	2	88	0	0	0	70038	69787	59715	25	40208	30106	10005	30267	10000	620856	3342350	1	49	68424	71470	71191	65191	139	65870	42858	32837	10874	65088	21746	71504	35	15	1	40201	100	99	100	10000	30100	10000	1	100	10040	4	0	10049	1	0	35924	10048	1	1	1	1	0	0	3003	2	191	3	3	71145	30141	9	6	9	10000	30100	71627	71648	71494	71505	71611
40204	71611	555	1	1	0	0	2	1	0	16	16	2258	1496	1	0	0	71845	70741	60319	512	40394	30308	10065	33004	10765	658569	3393973	1	49	68881	71868	71325	65402	215	66028	45002	34462	11036	68399	22658	72211	35	24	1	40201	100	99	100	10000	30100	10000	0	100	10067	4	1	10064	0	3	38171	10000	0	1	0	1	3	1	2610	2	71	2	2	71186	30113	9	6	6	10000	30100	71512	71499	71514	71509	71509
40204	71333	534	1	1	1	1	1	0	0	1	16	2120	1320	0	0	0	71509	70159	60225	25	40104	30106	10002	30100	10000	616032	3342494	1	49	66973	70041	70041	64637	12	65114	40100	30200	10439	63764	21646	71413	35	14	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10049	1	6	2252	10000	0	1	0	1	1	0	2610	2	17	2	2	69816	30006	9	6	0	10000	30100	70057	70042	70054	70057	70057
40204	70056	525	1	0	1	1	1	1	1	0	0	1	0	0	0	0	70026	69787	59715	25	40104	30103	10002	30100	10000	616059	3342494	0	49	66976	70056	70056	64652	3	64959	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10002	2	0	1	10000	0	1	1	1	0	0	2610	2	71	2	2	69816	30006	9	0	6	10000	30100	70057	70042	70057	70054	70057
40204	70041	524	1	0	0	0	1	0	0	0	0	2	0	0	1	1	70041	69787	59715	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70041	70054	64653	3	64961	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10002	0	1	1	10000	1	1	1	1	1	0	2610	2	71	2	2	69816	30003	6	6	9	10000	30100	70042	70057	70054	70079	70048
40204	70053	525	1	0	1	1	1	1	0	0	0	2	0	0	1	0	70041	69797	59719	25	40108	30103	10002	30100	10000	616078	3342350	1	49	66976	70041	70053	64637	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	1	10000	1	1	1	1	0	0	2610	2	71	2	2	69819	30006	0	0	0	10000	30100	70057	70057	70054	70042	70042
40204	70041	525	1	0	0	1	1	0	1	0	0	593	0	0	0	0	70041	69787	59701	25	40104	30103	10002	30100	10000	616311	3345182	1	49	66961	70056	70056	64637	3	64959	40100	30200	10000	60200	20000	70056	35	2	1	40201	100	99	100	10000	30100	10000	1	100	10002	1	1	10003	0	1	1	10000	1	1	1	1	1	0	2610	2	71	2	2	69819	30006	9	6	0	10000	30100	70057	70057	70057	70057	70057
40204	70056	525	1	0	0	0	0	1	0	0	0	1	0	0	1	0	70041	69787	59715	25	40108	30106	10002	30100	10000	616032	3345758	1	49	66976	70056	70056	64652	3	64959	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	2	2	1	10000	1	1	1	1	1	0	2610	2	71	2	2	69819	30006	0	9	9	10000	30100	70054	70057	70042	70042	70057
40204	70041	525	1	0	0	1	1	0	0	0	0	586	0	0	1	0	70041	69787	59715	25	40108	30103	10002	30100	10000	616032	3347726	1	49	66976	70056	70053	64637	3	64959	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	2	4	10000	0	1	0	1	0	0	2691	2	71	2	2	69816	30006	6	9	0	10000	30100	70042	70042	70042	70057	70057
40204	70056	542	1	0	0	1	0	0	1	0	0	2	0	0	0	0	70026	69702	59715	25	40104	30103	10002	30100	10000	616032	3346473	1	49	66961	70053	70041	64649	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	0	2610	2	71	2	2	69804	30003	0	9	9	10000	30100	70059	70054	70042	70054	70057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	1	2	1	1	0	70020	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	5	49	66967	0	70035	70047	64665	3	64974	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	0	0	6	71	4	5	69810	30003	0	6	6	10000	30010	70048	70075	70048	70048	70048
40024	70047	525	0	0	0	1	1	0	70032	69743	59706	25	40014	30013	10000	30010	10000	617068	3341470	1	0	49	66967	0	70047	70047	64665	3	65009	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	2520	0	0	6	71	3	6	69810	30003	6	6	6	10000	30010	70048	70048	70036	70048	70036
40024	70047	525	0	0	1	1	0	0	70020	69728	59706	25	40010	30013	10001	30010	10000	616952	3341470	0	5	49	66967	0	70035	70047	64653	3	65046	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	5	3	5	71	3	5	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	1	1	0	70032	69728	59706	25	40014	30013	10000	30010	10000	616952	3342062	1	5	49	66955	0	70047	70047	64665	3	64990	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	5	3	4	71	7	4	69810	30003	6	0	0	10000	30010	70048	70048	70048	70036	70048
40024	70047	524	0	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	5	49	66967	0	70047	70047	64665	3	65003	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	2520	5	3	2	71	3	3	69810	30003	6	6	6	10000	30010	70036	70048	70048	70036	70036
40024	70047	525	0	0	0	0	0	0	70032	69743	59706	25	40010	30013	10001	30010	10000	617068	3342062	1	5	49	66967	0	70047	70035	64653	3	65011	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	0	1	2520	0	0	5	71	4	4	69810	30000	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	1	1	0	70032	69743	59706	25	40014	30013	10000	30010	10000	616952	3342062	1	0	49	66968	0	70047	70047	64665	3	65009	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	1	0	0	2520	0	0	5	71	5	3	69810	30000	6	0	0	10000	30010	70048	70048	70036	70048	70048
40024	70035	525	0	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	617068	3342062	1	0	49	66967	3	70047	70047	64665	3	64987	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	5	3	4	71	4	3	69798	30003	6	6	6	10000	30010	70048	70036	70048	70048	70036
40024	70047	524	0	0	0	0	1	0	70032	69728	59706	25	40014	30010	10001	30010	10000	617068	3342062	1	5	49	66967	0	70047	70047	64653	3	65033	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	2520	5	3	3	71	4	4	69810	30003	0	6	6	10000	30010	70048	70048	70048	70048	70036
40024	70047	525	0	0	0	81	1	0	70032	69728	59706	25	40014	30013	10000	30010	10000	616952	3341470	1	5	49	66967	0	70047	70047	64665	3	64987	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	5	3	4	71	5	4	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	0	0	0	1	1	554	0	0	0	70042	69704	59702	25	40104	30103	10002	30100	10000	616811	3342381	1	49	66981	0	70059	70041	64673	3	64967	40125	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	0	0	1	10000	1	0	1	0	0	0	2637	1	71	1	1	69823	30003	13	10	13	10000	30100	70061	70061	70061	70061	70061
40204	70060	525	0	0	0	0	1	0	6	0	0	0	70039	69785	59713	25	40104	30103	10001	30100	10000	617076	3344073	0	49	66980	0	70060	70060	64663	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	1	1	10000	1	0	1	0	0	0	2610	1	71	1	1	69817	30003	10	10	13	10000	30100	70052	70055	70055	70055	70055
40204	70054	525	1	0	1	1	0	0	14	1	0	1	70045	69771	59762	75	40108	30147	10001	30256	10000	629821	3345230	0	49	66955	0	70057	70056	64654	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	1	1	0	0	2610	1	71	1	1	69823	30006	13	0	13	10000	30100	70061	70062	70061	70061	70042
40204	70044	525	0	0	0	0	0	1	13	0	0	0	70039	69767	59713	25	40100	30103	10001	30100	10000	617176	3344894	0	49	66980	0	70060	70060	64637	3	64963	40100	30200	10056	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	4	0	3	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30031	10	10	10	10000	30100	70061	70061	70061	70058	70061
40204	70057	524	0	1	0	0	0	0	1	0	0	0	70036	69785	59713	25	40104	30103	10001	30100	10000	616068	3347822	1	49	66977	0	70041	70060	64656	3	64960	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10001	0	1	1	10000	0	0	1	0	0	0	2610	1	71	1	1	69798	30003	13	13	13	10000	30100	70055	70055	70036	70055	70055
40204	70054	525	1	1	1	1	0	0	2	0	0	1	70045	69791	59716	25	40108	30106	10002	30125	10000	616708	3344702	0	49	66974	0	70054	70097	64647	3	64964	40125	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	0	10	0	10000	30100	70052	70036	70052	70036	70036
40204	70035	525	1	0	1	0	0	0	1	1	0	0	70026	69788	59724	25	40104	30106	10002	30100	10000	617473	3344798	0	49	66955	0	70035	70051	64647	3	64957	40125	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30003	10	10	10	10000	30100	70061	70058	70058	70058	70058
40204	70060	525	0	1	0	0	0	0	1	1	0	0	70039	69785	59710	25	40104	30100	10000	30100	10000	616068	3345550	1	49	66955	0	70035	70054	64657	3	64957	40100	30200	10000	60200	20000	70054	36	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	0	0	10000	0	0	3	10000	1	1	1	1	1	0	2610	1	71	1	1	69804	30006	13	10	10	10000	30100	70061	70042	70061	70061	70042
40204	70060	525	0	1	0	0	1	0	0	0	0	0	70039	69764	59764	25	40100	30103	10001	30100	10000	616068	3345849	1	49	66977	0	70041	70060	64656	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	1	1	10000	1	0	0	0	0	0	2610	1	71	1	1	69823	30003	13	0	0	10000	30100	70061	70042	70061	70061	70058
40204	70060	524	0	1	0	0	0	0	1	1	0	0	70039	69782	59713	25	40104	30103	10001	30100	10000	616068	3346222	0	49	66974	0	70035	70051	64638	3	64954	40125	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	13	10	10000	30100	70061	70042	70061	70042	70061

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	2	1	0	0	70073	69728	59706	25	40014	30013	10001	30010	10000	616997	3342062	1	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	2	71	5	7	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70052	524	1	0	0	1	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616970	3342062	0	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	165	10000	1	1	0	0	2520	4	71	4	4	69810	30003	0	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70050	525	0	0	1	1	0	0	70020	69728	59695	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	0	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	6	10000	1	1	0	0	2520	4	71	3	6	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70049	525	0	0	1	1	0	0	70032	69728	59695	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64665	3	65019	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	84	10000	1	0	0	0	2520	2	71	3	4	69810	30003	6	6	6	10000	30010	70048	70048	70036	70048	70048
40024	70051	525	0	0	1	1	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	9101	10003	1	1	0	0	2556	4	71	3	4	69810	30003	6	6	6	10000	30010	70036	70053	70048	70048	70048
40024	70048	524	0	0	1	1	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	0	0	2520	4	71	3	4	69798	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70048	524	0	0	1	1	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	81	10000	1	1	0	0	2520	4	71	4	3	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70049	525	0	0	1	1	0	0	70032	69728	59706	25	40014	30010	10001	30010	10000	616952	3342062	1	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	0	0	2520	4	71	4	2	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70049	525	0	0	1	1	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	0	0	2520	4	71	4	2	69810	30003	6	6	6	10000	30010	70048	70048	70036	70048	70048
40024	70052	524	0	0	1	1	0	0	70032	69728	59706	25	40014	30013	10002	30010	10000	616952	3342062	1	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10003	0	9056	10000	1	1	0	0	2520	4	71	3	4	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]
  ldr x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26736	200	1	1	0	0	0	45	1	0	0	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	42	80039	6	1	39	43	1	1	1	5118	3	16	3	2	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26732	200	1	1	0	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1166596	0	49	23647	26727	26727	16655	6	16723	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	3	80039	0	1	39	0	1	1	1	5118	3	16	3	3	26724	10	10	0	80000	100	26794	26728	26728	26708	26728
80204	26736	200	1	1	0	0	0	45	1	0	1	26712	0	12	12	16	25	80100	100	80000	100	80015	500	1177550	0	49	23647	26727	26727	16655	15	16679	80119	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	45	80000	6	1	39	43	1	1	1	5118	3	16	3	3	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	1	1	0	0	0	45	1	0	1	26712	2	12	12	0	25	80100	100	80000	100	80016	500	1167788	0	49	23627	26727	26727	16655	6	16679	80114	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	117	80039	6	0	39	43	1	1	1	5118	3	16	3	2	26724	10	0	4	80000	100	26728	26728	26728	26728	26728
80204	26727	201	1	1	0	0	0	45	1	0	1	26692	2	12	12	16	25	80100	100	80000	100	80016	500	1167481	0	49	23627	26727	26727	16635	6	16679	80115	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	132	80039	6	1	0	43	1	1	1	5118	3	16	3	3	26724	0	0	4	80000	100	26708	26728	26708	26728	26728
80204	26836	200	1	1	0	1	1	45	1	0	1	26692	2	0	12	16	25	80100	100	80000	100	80015	500	1164298	1	49	23647	26707	26707	16655	6	16659	80115	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	1	120	80033	6	1	39	43	1	1	1	5118	2	16	3	3	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26853	200	1	1	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80016	500	1167123	0	49	23627	26727	26707	16655	6	16679	80114	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	126	80039	6	0	39	43	1	1	1	5118	3	16	3	2	26724	10	0	0	80000	100	26728	26728	26728	26728	26728
80204	26845	200	1	1	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167222	0	49	23647	26727	26868	16645	9	16666	80121	200	80030	200	160060	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	138	80039	6	1	39	43	2	2	2	5129	4	23	5	5	26724	10	10	4	80000	100	26729	26728	26728	26728	26729
80204	26728	200	1	1	0	0	0	45	1	0	1	26712	2	0	12	16	25	80100	100	80000	100	80019	500	1171109	0	49	23628	26727	26727	16645	10	16667	80121	200	80030	200	160060	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	123	80039	6	1	39	43	2	2	2	5128	5	23	5	5	26724	10	10	4	80000	100	26729	26728	26728	26728	26729
80204	26836	200	1	1	0	0	0	46	1	0	1	26712	2	12	12	0	25	80100	100	80000	100	80020	500	1164830	1	49	23647	26728	26708	16625	9	16666	80121	200	80030	200	160060	26708	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	120	80039	6	1	39	43	2	2	2	5129	5	23	5	5	26724	10	0	4	80000	100	26728	26709	26729	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26723	200	0	0	0	0	0	0	0	41	0	1	0	2	26712	2	0	12	5	25	80010	10	80000	10	80000	50	1166750	49	23801	26708	26727	16652	3	16688	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80035	1	39	80039	6	1	0	0	0	5020	1	16	1	1	26705	10	0	2	80000	10	26729	26971	26722	26868	26728
80024	26727	200	0	1	0	0	1	0	0	45	0	0	0	2	26712	2	0	18	16	25	80010	10	80000	10	80000	50	1166886	49	23651	26723	26728	16652	3	16707	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	3	39	80000	6	1	0	43	0	5020	1	16	1	1	26724	10	0	2	80000	10	26728	26741	26733	26750	26742
80024	26727	200	0	0	0	0	0	0	0	45	0	0	0	2	26712	0	18	18	129	25	80010	10	80000	10	80000	50	1167491	49	23628	26708	26708	16652	3	16702	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	39	0	80039	0	0	80000	6	0	35	39	0	5020	1	16	1	1	26719	10	10	4	80000	10	26729	26983	26735	26828	26728
80024	26708	200	0	0	0	0	0	0	0	0	0	0	0	2	26693	2	18	18	19	25	80010	10	80000	10	80000	50	1167605	49	23628	26722	26708	16652	3	16708	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80000	4	0	80039	6	0	35	0	0	5020	1	16	1	1	26725	10	10	4	80000	10	26728	26955	26735	26875	26729
80024	26728	200	0	0	0	0	0	0	0	80	0	1	0	0	26712	2	12	12	20	74	80010	10	80000	10	80000	50	1166750	49	23647	26708	26722	16652	3	16822	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	42	80035	6	0	39	0	0	5020	1	16	1	1	26719	0	6	0	80000	10	26709	26967	26737	26836	26728
80024	26880	201	0	0	0	0	0	0	0	45	0	0	0	2	26693	2	18	12	16	25	80010	10	80000	10	80000	50	1167077	49	23648	26728	26727	16672	3	16688	80010	20	80000	20	160000	26734	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	1	39	80000	6	0	0	0	0	5020	1	16	1	1	26728	0	10	4	80000	10	26709	26980	26741	26792	26709
80024	26727	200	0	0	0	0	0	0	0	63	0	0	0	1	26716	2	18	0	4	25	80010	10	80000	10	80000	50	1166993	49	23646	26731	26884	16667	3	16707	80010	20	80000	20	160000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	4	39	0	80039	0	0	80000	6	0	0	39	0	5020	1	16	1	1	26725	0	6	4	80000	10	26728	26921	26764	26731	26721
80024	26727	200	0	0	0	0	0	0	0	0	0	0	0	2	26716	0	0	18	83	25	80010	10	80000	10	80000	50	1168843	49	23642	26722	26722	16652	3	16702	80010	20	80000	20	160000	26708	72	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80035	0	39	80035	6	0	35	43	0	5020	1	16	1	1	26724	0	10	2	80000	10	26709	26867	26770	26736	26741
80024	26708	200	0	0	0	0	1	0	0	0	0	1	0	2	26713	2	18	12	116	25	80010	10	80260	10	80000	50	1166993	49	23642	26722	26722	16652	3	16688	80010	20	80000	20	160000	26712	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80035	0	0	80039	6	0	35	0	2	5020	1	16	1	1	26705	10	6	4	80000	10	26729	26986	26739	26839	26728
80024	26727	200	0	0	0	0	1	0	0	9	0	0	0	2	26693	2	18	18	15	25	80010	10	80000	10	80000	50	1168843	49	23648	26722	26722	16672	3	16688	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80035	0	39	80039	6	0	0	43	0	5020	1	16	1	1	26705	6	10	0	80000	10	26729	26987	26719	26803	26728

LDR (register, uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations