Firestorm: LDUR (32-bit) measurements

Code:

  ldur w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	398	3	0	1	0	0	60	0	0	1	383	17	15	30	17	25	1000	1000	1000	15288	399	398	220	3	256	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	54	43	73	6	16	6	6	395	6	6	3	1000	399	399	400	400	399
1004	398	2	1	1	0	0	60	0	0	1	385	17	15	30	17	25	1000	1000	1000	15284	398	398	220	3	256	1000	1000	1000	401	81	1	1	1001	1000	1000	1	1000	58	1054	54	1054	6	1	54	43	73	6	16	6	6	396	6	6	3	1000	399	399	399	402	399
1004	398	3	0	0	0	0	61	0	0	1	384	17	15	30	17	25	1000	1000	1000	15284	398	398	220	3	256	1000	1000	1000	398	81	1	1	1001	1000	1000	1	1000	58	1054	54	1054	6	1	54	43	73	5	16	7	6	395	6	6	3	1000	399	399	399	399	399
1004	398	3	0	0	0	0	60	1	0	1	383	17	15	30	17	25	1000	1000	1000	15284	398	398	220	3	256	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	54	43	73	6	16	6	6	395	6	6	3	1000	399	400	399	399	400
1004	398	2	0	0	0	0	60	1	0	1	383	17	15	30	17	25	1000	1000	1000	15305	398	398	220	3	257	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	55	43	73	6	16	6	7	395	6	6	3	1000	399	399	399	399	399
1004	398	3	0	0	0	0	60	1	0	1	383	17	15	30	17	25	1000	1000	1000	15284	398	398	221	3	256	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	54	43	73	6	16	6	6	395	6	6	3	1000	399	399	399	399	399
1004	398	3	0	0	0	0	60	0	0	1	383	18	15	30	17	25	1000	1000	1000	15284	398	398	220	3	256	1000	1000	1000	398	83	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	54	43	73	6	16	6	6	395	6	6	3	1000	399	399	399	400	399
1004	398	3	0	0	0	0	60	0	0	1	383	17	15	30	17	25	1000	1000	1000	15284	398	398	220	3	256	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	54	43	73	5	16	6	6	398	6	6	3	1000	399	399	399	399	402
1004	398	3	0	0	0	0	60	1	0	1	383	17	15	30	17	25	1000	1000	1000	15312	398	398	221	3	258	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1054	6	1	54	43	73	6	16	6	6	395	6	6	3	1000	399	399	399	399	399
1004	398	3	0	0	0	0	63	1	0	1	383	17	15	30	16	25	1000	1000	1000	15312	398	398	220	3	256	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1000	58	1054	54	1055	6	1	54	43	73	6	16	6	5	395	6	6	3	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldur w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	1	1	1	0	0	0	0	1	0	1	0	0	70038	69784	59712	25	40108	30103	10002	30100	10000	616078	3342350	0	49	66961	0	70053	70041	64652	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	2	1	10002	0	2	4	10000	1	1	1	1	1	0	2610	2	71	1	1	69804	30006	0	6	0	10000	30100	70055	70110	70060	70054	70054
40204	70053	525	1	0	1	0	0	0	1	2	0	0	0	0	70038	69784	59712	25	40108	30103	10001	30100	10000	616032	3342350	0	49	66973	0	70053	70053	64651	3	64944	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	0	10001	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	0	10000	30100	70054	70054	70054	70054	70054
40204	70053	525	1	1	1	0	0	0	0	1	0	0	0	1	70041	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	0	49	66973	0	70053	70053	64637	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10002	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69816	30003	6	0	6	10000	30100	70073	70043	70054	70054	70054
40204	70053	525	1	1	0	0	0	0	0	2	0	0	0	1	70026	69786	59712	25	40108	30103	10002	30100	10000	616032	3342350	0	49	66973	0	70053	70053	64649	3	64944	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	2	1	10002	0	1	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69804	30003	0	6	6	10000	30100	70054	70054	70054	70054	70057
40204	70041	524	1	0	1	0	0	0	0	2	0	1	0	0	70038	69784	59712	25	40108	30106	10001	30100	10000	616032	3342350	0	49	66961	0	70053	70053	64649	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	1	1	10001	0	1	4	10000	1	1	1	1	2	0	2610	1	71	1	1	69816	30006	6	0	6	10000	30100	70042	70054	70054	70054	70042
40204	70053	525	1	0	0	0	0	0	0	1	0	1	0	1	70026	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	0	70053	70053	64649	3	64956	40100	30200	10000	60596	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10002	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70074	70060	70056	70054	70054
40204	70053	525	1	0	1	0	0	1	0	1	0	1	0	1	70026	69702	59712	25	40104	30106	10002	30100	10000	616078	3342350	0	49	66973	0	70041	70053	64649	3	64956	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10002	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70042	70054	70054	70054
40204	70053	525	1	0	1	0	0	0	0	2	0	0	0	0	70038	69702	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	63939	0	70053	70041	64649	3	64956	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	0	10002	0	1	1	10000	1	1	0	1	0	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70045	70042	70054	70054	70054
40205	70041	524	1	1	1	0	0	0	0	2	0	0	0	1	70038	69702	59701	25	40104	30106	10002	30100	10000	616032	3341769	0	49	66973	0	70041	70149	64649	3	64944	40100	30200	10000	60200	10000	70062	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10001	0	1	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69816	30006	6	0	6	10000	30100	70054	70054	70054	70042	70057
40204	70041	524	1	1	1	0	0	0	0	2	0	1	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616078	3342350	1	49	66973	0	70053	70053	64637	3	64944	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	0	10001	0	2	1	10000	0	1	1	1	0	0	2610	1	71	1	1	69816	30006	0	0	6	10000	30100	70054	70042	70054	70042	70054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	1	1	1	1	0	1	0	2	0	0	0	0	70026	69784	59719	25	40014	30016	10002	30010	10000	616995	3342686	0	49	66961	70057	70041	64678	3	64983	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	2	1	10001	1	1	5	10000	1	1	1	1	0	0	0	2520	0	7	71	6	5	69820	30006	0	10	10	10000	30010	70061	70042	70061	70061	70061
40024	70057	524	1	0	0	1	0	0	0	2	0	0	0	0	70049	69784	59701	25	40018	30016	10001	30010	10000	617072	3347090	0	49	66980	70057	70060	64678	3	64985	40010	30215	10000	60020	10000	70044	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	0	0	2520	0	5	71	6	5	69823	30003	13	10	13	10000	30010	70042	70102	70094	70068	70062
40024	70041	525	1	0	0	1	0	0	0	2	0	1	0	0	70045	69702	59701	25	40018	30016	10002	30010	10000	617072	3342686	0	49	66980	70041	70057	64678	3	64966	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10001	0	2	1	10000	1	1	1	1	2	0	0	2520	0	6	71	6	5	69823	30006	10	10	0	10000	30010	70058	70042	70061	70061	70042
40024	70060	525	1	0	0	0	0	0	0	7	0	0	0	0	70045	69784	59719	25	40014	30016	10001	30010	10000	617072	3341769	0	49	66980	70041	70060	64675	3	64966	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	1	10002	0	0	1	10000	1	1	1	1	1	0	0	2520	0	6	71	5	5	69820	30006	0	10	10	10000	30010	70061	70061	70061	70061	70061
40024	70060	525	1	0	0	0	0	0	0	2	0	0	0	0	70026	69781	59719	25	40014	30016	10002	30010	10000	617072	3342686	0	49	66985	70060	70060	64678	3	64966	40218	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	1	10001	0	0	1	10000	1	1	0	1	0	0	0	2520	0	5	71	5	6	69823	30006	0	10	0	10000	30010	70058	70061	70061	70061	70058
40024	70057	524	1	0	1	1	0	0	0	1	0	1	0	1	70026	69784	59716	25	40018	30016	10005	30010	10000	617072	3342686	0	49	66980	70057	70060	64683	3	64985	40010	30020	10000	60020	10000	70065	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	0	10002	0	0	1	10000	1	1	1	1	0	0	0	2520	0	6	71	6	5	69823	30006	13	0	0	10000	30010	70061	70042	70061	70061	70061
40024	70060	524	1	0	1	1	1	0	0	2	0	0	0	0	70042	69781	59716	25	40018	30016	10002	30010	10000	617072	3342686	0	49	66980	70057	70057	64678	3	64985	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	1	10001	0	2	1	10000	1	1	0	1	1	0	0	2520	0	5	71	6	6	69823	30006	0	10	10	10000	30010	70051	70061	70042	70061	70061
40024	70060	524	1	0	1	1	0	0	0	1	0	0	0	1	70026	69702	59719	25	40018	30016	10001	30010	10057	616995	3342686	0	49	66977	70057	70060	64659	3	64966	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	3	0	10001	0	0	1	10000	1	1	0	1	2	0	0	2520	0	5	71	6	6	69823	30003	13	10	10	10000	30010	70061	70042	70058	70058	70061
40024	70057	525	1	1	1	1	0	0	0	2	0	1	0	1	70026	69784	59701	25	40018	30013	10002	30010	10000	617072	3341769	0	49	66980	70057	70060	64678	3	64985	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	1	10001	11	2	1	10000	1	1	1	1	2	0	0	2520	0	5	71	6	6	69820	30003	0	10	0	10000	30010	70061	70061	70058	70061	70058
40024	70060	525	1	0	1	0	1	0	0	2	0	0	0	0	70046	69784	59701	25	40014	30016	10001	30010	10000	617045	3342542	0	49	64030	70059	70124	64675	3	64982	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	1	10001	0	0	1	10000	1	1	1	1	1	0	0	2520	0	6	71	6	5	69823	30003	10	10	10	10000	30010	70042	70061	70061	70042	70058

Test 3: throughput

Count: 8

Code:

  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]
  ldur w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26722	200	0	1	41	1	0	1	26707	0	18	18	6	25	80100	100	80000	100	80000	500	1168388	1	49	23642	26722	26707	16645	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	2	35	80035	6	1	35	39	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26776	26822	26724	26734
80204	26732	200	0	1	41	1	0	1	26707	0	18	18	15	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26707	26722	16645	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	2	35	80035	6	1	0	39	5110	1	16	1	1	26704	6	6	2	80000	100	26723	26723	26708	26723	26726
80204	26722	201	0	0	41	0	0	0	26707	2	18	18	11	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26722	26710	16649	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80035	0	35	80036	6	1	35	39	5110	1	16	1	1	26719	6	0	2	80000	100	26723	26811	26805	26724	26733
80204	26722	200	0	0	50	1	0	1	26707	2	18	0	2	25	80100	100	80000	100	80000	500	1159747	1	49	23645	26722	26722	16645	3	16680	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	1	35	80035	6	1	35	39	5110	1	16	1	1	26719	6	0	2	80000	100	26723	26808	26832	26728	26732
80204	26722	200	0	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1166525	0	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	3	35	80035	0	1	0	39	5110	1	16	1	1	26719	6	6	0	80000	100	26723	26791	26815	26729	26739
80204	26707	200	0	0	41	0	1	1	26707	2	18	0	2	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80035	3	35	80035	6	1	35	39	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26778	26814	26725	26878
80204	26725	200	0	0	41	0	0	1	26707	2	18	0	12	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26722	26722	16630	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	1	35	80035	0	0	35	39	5110	1	16	1	1	26719	0	6	2	80000	100	26723	26845	26819	26725	26728
80204	26707	200	0	0	41	0	1	1	26714	2	18	18	17	25	80100	100	80000	100	80000	500	1166818	1	49	23642	26722	26722	16630	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	1	35	80035	6	1	35	39	5110	1	16	1	1	26719	6	6	0	80000	100	26723	26723	26729	26737	26725
80204	26729	200	0	0	0	0	1	1	26707	2	18	18	3	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	3	35	80035	0	1	35	0	5110	1	16	1	1	26719	6	0	2	80000	100	26723	26833	26799	26725	26723
80204	26730	200	0	0	41	0	1	1	26692	2	18	18	13	25	80100	100	80000	100	80000	500	1166525	1	49	23642	26722	26722	16645	3	16665	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	5	35	80036	0	1	35	39	5110	1	16	1	1	26719	0	6	2	80000	100	26723	26858	26811	26726	26738

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26738	215	1	0	0	0	0	80	1	0	3	26710	2	0	0	17	25	80010	10	80000	10	80000	50	1167734	0	49	23639	0	26735	26736	16682	3	16718	80010	20	80000	20	80000	26735	82	1	1	80021	10	9	10	80000	10	80000	1	10	80020	19	0	80057	1	1	0	62	80038	6	1	57	42	19	0	0	5020	9	16	6	11	26734	9	9	0	80000	10	26739	26720	26738	26738	26735
80024	26732	214	1	1	0	0	1	65	1	0	2	26812	0	0	18	1	25	80010	10	80000	10	80000	50	1170204	0	49	23652	0	26715	26732	16677	3	16695	80010	20	80000	20	80000	26733	81	1	1	80021	10	9	10	80000	10	80000	0	10	80021	19	0	80057	0	0	1	62	80037	6	1	57	0	19	1	1	5020	15	16	11	11	26729	9	9	2	80000	10	26715	26733	26715	26733	26733
80024	26715	215	1	0	0	0	0	65	1	0	2	26838	2	18	18	15	25	80010	10	80000	10	80000	50	1167660	0	49	23652	0	26714	26732	16678	3	16713	80010	20	80000	20	80000	26714	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80057	1	2	1	62	80038	6	1	57	42	19	0	0	5020	6	16	8	7	26729	9	0	2	80000	10	26726	26718	26733	26716	26715
80024	26732	207	1	0	1	0	1	21	0	0	1	26717	2	0	18	16	25	80010	10	80000	10	80000	50	1167660	0	49	23661	0	26745	26715	16684	3	16713	80010	20	80000	20	80000	26714	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80019	0	0	0	21	80000	6	1	57	42	19	1	0	5020	7	16	6	11	26729	0	0	0	80000	10	26733	26733	26715	26715	26734
80024	26733	207	1	1	0	0	0	65	0	0	0	26723	2	0	18	16	25	80010	10	80000	10	80000	50	1167660	0	49	23652	0	26714	26732	16660	3	16695	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80021	20	0	80019	0	0	1	21	80000	6	1	57	42	19	1	0	5020	7	16	7	13	26729	0	9	2	80000	10	26715	26733	26733	26716	26734
80024	26733	207	1	0	0	0	0	21	0	0	2	26814	2	18	0	16	25	80010	10	80000	10	80000	50	1167660	0	49	20672	0	26734	26732	16660	3	16695	80010	20	80000	20	80000	26732	82	1	1	80021	10	9	10	80000	10	80000	1	10	80020	20	0	80057	1	0	0	21	80038	6	0	57	0	19	2	0	5020	13	16	11	8	26712	9	9	0	80000	10	26715	26733	26733	26716	26734
80024	26733	204	1	1	1	0	0	66	1	0	3	26844	2	0	0	15	25	80010	10	80000	10	80000	50	1167599	0	49	23635	0	26732	26715	16677	3	16694	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80058	1	0	1	21	80038	0	0	57	42	19	1	0	5020	5	16	6	7	26712	9	9	2	80000	10	26734	26716	26715	26733	26716
80024	26715	204	1	1	0	0	0	21	1	0	3	26844	2	18	18	15	25	80010	10	80000	10	80000	50	1167299	0	49	23653	0	26735	26715	16679	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80057	1	0	0	59	80168	0	1	57	0	19	0	0	5020	8	16	7	6	26729	9	9	2	80000	10	26733	26733	26733	26716	26716
80024	26733	206	1	0	0	0	0	23	0	0	0	26811	2	18	18	1	25	80010	10	80000	10	80000	50	1170204	0	49	23827	0	26718	26719	16681	3	16712	80010	20	80000	20	80000	26732	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	21	42	80019	1	1	1	21	80000	0	0	57	42	19	2	0	5020	6	16	6	13	26712	9	0	2	80000	10	26716	26715	26733	26715	26716
80024	26732	200	1	1	1	0	0	65	1	0	3	26813	0	18	0	15	25	80010	10	80000	10	80000	50	1167660	0	49	23652	0	26714	26732	16678	3	16713	80010	20	80000	20	80000	26732	64	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80057	0	0	1	59	80038	0	1	57	0	19	0	0	5020	9	16	9	8	26712	9	9	0	80000	10	26733	26733	26733	26733	26715

LDUR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations