Firestorm: LDURH measurements

Code:

  ldurh w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	1	1	41	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	1	389	391	212	3	247	1000	1000	1000	389	72	1	1	1001	1000	1000	1000	39	1035	35	1035	6	1	35	39	73	1	16	1	1	387	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	1	1	41	0	0	1	374	2	18	18	11	25	1000	1000	1000	14844	1	389	389	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	1000	39	1035	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	392	390	390	390	390
1004	389	2	0	0	1	1	41	0	0	1	374	2	18	18	11	25	1000	1000	1000	14838	1	389	392	212	3	247	1000	1000	1000	391	71	1	1	1001	1000	1000	1000	39	1039	39	1039	6	1	39	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	2	0	0	1	1	45	0	0	2	379	2	12	18	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	39	1039	39	1039	6	1	39	39	73	1	16	1	1	391	10	6	2	1000	395	395	396	390	395
1004	394	3	0	0	1	0	42	0	0	2	379	2	12	12	16	25	1000	1000	1000	17219	0	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	39	1039	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	395	395	390	390	395
1004	394	2	0	0	1	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	39	1039	39	1039	6	1	36	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	1	0	50	1	0	2	379	2	12	12	16	25	1000	1000	1000	15018	0	388	389	217	3	252	1000	1000	1000	394	72	1	1	1001	1000	1000	1000	39	1039	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	1	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	39	1039	39	1035	6	1	35	39	73	1	16	1	1	386	10	6	4	1000	398	395	395	395	395
1004	394	3	0	0	1	0	41	0	0	2	379	2	18	12	22	25	1000	1000	1000	15037	0	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	39	1039	39	1039	6	1	35	43	73	1	16	1	1	386	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	1	0	45	1	0	1	379	2	12	18	16	25	1000	1000	1000	14774	0	394	394	217	3	252	1000	1000	1000	389	71	1	1	1001	1000	1000	1000	39	1039	39	1035	6	1	39	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldurh w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	524	1	0	0	0	0	1	0	1	0	70036	69764	59713	25	40104	30103	10001	30100	10000	616175	3342254	0	49	66997	70051	70051	64647	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	1	2610	3	71	2	2	69814	30003	10	10	10	10000	30100	70052	70036	70055	70036	70055
40204	70053	525	0	0	0	0	0	12	0	1	0	70039	69785	59713	25	40104	30103	10001	30100	10000	616175	3341470	0	49	66957	70058	70051	64647	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10005	0	1	10000	0	0	10000	1	1	1	2610	2	71	2	2	69814	30003	13	13	0	10000	30100	70055	70036	70036	70055	70036
40204	70054	525	0	1	1	0	0	1	0	0	0	70039	69764	59713	25	40100	30103	10001	30100	10000	616041	3342398	0	49	66955	70054	70054	64650	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	3	10000	1	1	0	2610	2	71	2	2	69814	30003	13	10	13	10000	30100	70036	70036	70052	70055	70055
40204	70054	525	0	0	0	0	0	1	0	0	0	70039	69785	59710	25	40100	30103	10001	30100	10000	616041	3342398	0	49	67006	70054	70035	64650	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	1	2610	2	71	2	2	69798	30003	13	13	13	10000	30100	70036	70055	70055	70036	70055
40204	70054	524	0	0	0	0	0	1	0	0	0	70039	69785	59710	25	40104	30100	10001	30100	10000	616041	3342398	0	49	67022	70054	70035	64650	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	10000	0	1	1	2610	2	71	2	2	69814	30003	13	13	10	10000	30100	70055	70055	70052	70055	70036
40204	70035	524	0	0	0	0	0	0	0	1	0	70039	69896	59716	25	40104	30103	10000	30100	10000	616041	3342398	0	49	67033	70035	70054	64650	3	64938	40100	30200	10000	60200	10000	70396	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	1	1	2610	2	71	2	2	69798	30000	13	0	10	10000	30100	70036	70055	70052	70055	70055
40204	70054	525	0	0	0	0	0	1	0	0	0	70020	69782	59713	25	40104	30103	10000	30100	10000	616041	3342398	0	49	67069	70075	70037	64631	3	64957	40878	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	9	10000	1	1	1	2610	2	71	2	2	70118	30003	13	13	13	10000	30100	70055	70055	70036	70052	70038
40204	70054	524	0	0	0	0	0	1	0	1	0	70036	69782	59695	25	40100	30103	10001	30100	10000	616041	3342398	0	49	67006	70035	70054	64650	3	64968	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	2610	2	71	2	2	69798	30003	13	13	13	10000	30100	70055	70055	70036	70036	70036
40204	70054	525	0	0	0	0	0	6	0	0	0	70039	69792	59695	25	40104	30103	10001	30100	10000	616175	3341470	0	49	66958	70054	70054	64650	3	64957	40100	30200	10000	60200	10000	70244	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	1	2610	3	71	2	2	69817	30000	0	13	13	10000	30100	70055	70052	70055	70055	70055
40204	70035	525	0	0	0	0	0	1	0	0	1	70039	69764	59713	25	40104	30103	10000	30100	10000	616014	3342398	0	49	66956	70035	70035	64650	37	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	10000	1	1	1	2610	2	71	2	2	69817	30003	10	10	13	10000	30100	70055	70052	70055	70036	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	1	0	0	1	0	2	0	1	0	1	70026	69784	59716	25	40018	30016	10002	30010	10000	616991	3342254	0	1	49	66971	70051	70051	64672	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10003	0	2	1	10000	1	1	0	1	1	2520	0	0	0	8	71	0	0	0	6	8	69814	30003	0	10	10	10000	30010	70052	70036	70052	70036	70052
40024	70051	524	0	0	0	0	0	0	0	1	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	617068	3342254	0	1	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10003	0	1	1	10000	1	1	1	1	0	2520	0	0	0	5	71	0	0	1	6	5	69817	30000	10	0	0	10000	30010	70052	70055	70052	70052	70052
40024	70051	525	0	0	0	0	0	1	0	1	0	0	70036	69784	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	1	49	66955	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	2	1	10000	1	1	1	1	2	2520	0	0	0	6	71	0	0	0	10	7	69889	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	524	0	0	0	0	0	1	0	1	0	0	70036	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	1	49	66971	70035	70035	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	0	0	0	5	71	0	0	0	6	6	69814	30003	10	10	13	10000	30010	70052	70052	70036	70052	70052
40024	70051	525	0	0	0	0	0	1	0	1	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	0	1	49	66961	70057	70057	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	2520	0	0	0	6	71	0	0	0	6	6	69820	30003	10	0	13	10000	30010	70058	70058	70058	70042	70042
40024	70058	525	1	0	1	1	0	2	0	1	0	0	70036	69775	59710	25	40014	30013	10000	30010	10000	616991	3342254	0	1	49	66971	70051	70051	64653	3	64976	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	2520	0	0	0	5	71	0	0	0	6	6	69814	30003	10	10	10	10000	30010	70052	70052	70036	70052	70036
40024	70051	525	0	0	0	0	0	1	0	0	0	1	70042	69784	59716	25	40018	30016	10002	30010	10000	616995	3342542	0	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	0	0	0	6	71	0	0	0	5	6	69814	30003	10	10	10	10000	30010	70052	70064	70052	70052	70052
40024	70051	525	0	0	0	0	0	1	0	1	0	1	70036	69775	59710	25	40014	30010	10000	30010	10000	616991	3342254	0	1	49	66955	70035	70051	64672	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10004	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	0	0	0	7	71	0	0	0	5	6	69820	30006	10	10	10	10000	30010	70058	70042	70042	70058	70042
40024	70057	525	1	0	0	1	0	1	0	1	0	0	70036	69775	59695	25	40014	30013	10000	30010	10000	616991	3342302	1	1	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	0	0	0	6	71	0	0	0	5	6	69820	30006	10	10	10	10000	30010	70058	70058	70042	70058	70060
40024	70057	525	1	0	0	0	0	2	0	1	0	0	70036	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	1	49	66955	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10002	0	2	1	10000	1	1	1	1	1	2520	0	0	0	6	71	0	0	0	5	7	69814	30003	0	10	24	10000	30010	70058	70058	70058	70058	70058

Test 3: throughput

Count: 8

Code:

  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]
  ldurh w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	0	1	0	1	0	1	0	0	65	0	1	0	3	26721	2	18	18	16	25	80100	100	80000	100	80015	500	1167107	0	49	23653	26736	26714	16664	6	17027	80114	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	42	0	80019	0	0	0	59	80000	6	0	18	42	19	0	1	1	1	5118	0	16	0	0	26729	9	0	2	80000	100	26733	26733	26715	26715	26715
80204	26714	201	0	1	1	1	1	0	0	0	65	0	1	0	2	26723	2	18	18	0	25	80100	100	80130	100	80178	500	1182371	0	49	23652	26733	26732	16655	3	16690	80100	200	80000	200	80000	26733	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	0	80057	0	0	0	59	80037	6	1	19	42	19	1	0	0	0	5110	1	16	1	1	26729	0	9	0	80000	100	26733	26734	26733	26733	26733
80204	26734	200	0	1	1	1	1	0	0	0	65	0	0	0	3	26731	0	18	18	0	25	80100	100	80000	100	80000	500	1166758	0	49	23652	26732	26732	16655	3	16672	80100	200	80000	200	80000	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	0	0	80057	0	0	1	62	80038	6	1	57	0	19	1	0	0	0	5110	1	16	1	1	26729	9	9	2	80000	100	26715	26715	26733	26715	26734
80204	26732	200	0	1	1	1	0	0	0	0	83	0	0	0	2	26717	0	0	18	92	25	80100	100	80000	100	80000	500	1166758	0	49	23634	26718	26736	16659	3	16672	80100	200	80000	200	80000	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	0	80019	0	0	1	59	80000	6	1	57	42	19	1	0	0	0	5110	1	16	1	1	26711	9	9	2	80000	100	26733	26733	26715	26715	26733
80204	26732	200	0	1	0	1	1	0	0	0	21	0	0	0	2	26717	2	0	18	1	25	80100	100	80000	100	80000	500	1166519	0	49	23653	26714	26732	16655	3	16690	80100	200	80000	200	80000	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	0	80057	1	1	3	65	80038	0	1	19	42	19	2	0	0	0	5110	1	16	1	1	26711	0	9	2	80000	100	26734	27336	26733	26719	26734
80204	26714	200	0	1	0	1	0	0	0	0	113	0	0	0	3	26699	2	0	0	1	25	80100	100	80000	100	80000	500	1169676	0	49	23634	26733	26733	16655	3	16690	80100	200	80000	200	80000	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	0	0	80057	0	0	2	21	80037	6	0	56	42	19	1	0	0	0	5110	1	16	1	1	26733	0	0	2	80000	100	26733	26715	26733	26715	26733
80204	26714	200	0	1	1	1	0	0	0	0	65	0	0	0	3	26699	2	18	18	15	25	80100	100	80000	100	80000	500	1159120	0	49	23955	26745	26733	16637	3	16690	80100	200	80000	200	80000	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	0	0	80019	0	0	1	59	80000	6	0	57	42	19	0	0	0	0	5110	1	16	1	1	26729	9	0	2	80000	100	26715	26733	26734	26715	26715
80204	26732	200	0	1	1	0	0	0	0	0	22	0	0	0	2	26699	0	18	18	16	25	80100	100	80000	100	80000	500	1169486	0	49	23652	26733	26732	16637	3	16690	80100	200	80000	200	80000	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	0	0	80057	1	0	0	62	80000	6	0	19	42	19	0	0	0	0	5110	1	16	1	1	26729	0	0	2	80000	100	26734	26733	26733	26733	26734
80204	26733	200	0	1	1	1	0	0	0	0	21	0	0	0	2	26699	0	18	0	16	25	80100	100	80000	100	80000	500	1166519	0	49	23652	26714	26732	16637	3	16690	80100	200	80000	200	80000	26714	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	0	0	80057	0	0	1	21	80038	6	1	57	0	19	0	0	0	0	5110	1	16	1	1	26729	9	9	2	80000	100	26733	26733	26734	26715	26733
80204	26732	200	0	1	0	1	1	1	1	0	65	0	0	0	1	26720	2	18	18	16	25	80100	100	80000	100	80000	500	1167685	1	49	23634	26714	26714	16655	3	16672	80100	200	80000	200	80000	26715	81	1	1	80201	100	99	100	80000	100	80000	1	100	80021	20	42	0	80056	1	0	2	59	80000	6	1	19	0	19	1	0	0	0	5110	1	16	1	1	26729	9	9	2	80000	100	26715	26734	26734	26715	26734

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	0	0	1	0	0	1	66	1	0	3	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1172009	0	1	49	23656	0	26736	26737	16659	3	16716	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80059	1	0	0	21	80040	6	0	39	43	0	0	5020	0	0	1	16	4	0	1	1	26727	10	10	4	80000	10	26728	26728	26729	26729	26709
80024	26728	200	0	0	0	0	0	0	45	0	0	1	26693	0	0	1	16	25	80010	10	80000	10	80000	50	1166750	0	1	49	23648	0	26727	26727	16672	3	16707	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80058	0	1	2	61	80000	6	1	39	43	0	0	5020	0	0	1	16	2	0	1	1	26725	10	0	4	80000	10	26728	26709	26729	26709	26728
80024	26708	200	0	0	0	0	0	0	44	1	0	1	26712	0	0	0	16	25	80010	10	80000	10	80000	50	1166750	0	1	49	23648	0	26728	26708	16672	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80059	0	0	0	60	80040	6	1	39	44	0	0	5020	0	0	1	16	2	0	1	1	26705	10	10	0	80000	10	26729	26732	26709	26728	26709
80024	26728	200	0	0	0	0	0	0	0	1	0	0	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	1	1	49	23648	0	26727	26727	16672	3	16707	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80020	21	43	0	80059	1	0	0	61	80000	0	1	39	43	0	0	5020	0	0	1	16	2	0	1	1	26724	0	10	4	80000	10	26709	26732	26732	26732	26728
80024	26729	200	0	0	0	0	0	0	0	0	0	1	26713	0	0	12	16	48	80010	10	80130	10	80000	50	1167501	1	1	49	23647	0	26731	26731	16676	3	16711	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	0	0	80059	1	0	0	61	80039	6	0	39	43	0	0	5020	1	0	1	16	0	0	1	1	26730	10	10	0	80000	10	26729	26709	26709	26728	26709
80024	26728	200	0	0	0	0	0	0	45	0	0	1	26716	2	1	1	0	25	80010	10	80000	10	80000	50	1166750	0	0	49	23669	0	26727	26728	16652	3	16708	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	0	0	80059	0	0	2	61	80000	0	1	38	43	0	0	5020	0	0	1	16	2	0	1	1	26724	10	10	4	80000	10	26732	26709	26733	26729	26729
80024	26728	200	0	0	0	0	0	0	45	0	0	0	26713	2	1	12	16	25	80010	10	80000	10	80000	50	1166750	0	0	49	23648	0	26727	26708	16672	3	16707	80010	20	80000	20	80000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	0	0	80058	1	0	1	64	80040	6	1	0	43	0	0	5020	0	0	1	16	2	0	1	1	26724	0	10	4	80000	10	26729	26729	26728	26728	26709
80024	26708	200	0	0	0	0	0	0	44	0	0	1	26713	0	0	12	0	25	80010	10	80000	10	80000	50	1168843	0	0	49	23648	0	26728	26708	16676	3	16708	80010	20	80000	20	80000	26730	77	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80059	0	0	2	21	80040	6	1	39	43	0	0	5020	0	0	1	16	2	0	1	1	26728	0	10	0	80000	10	26728	26729	26709	26709	26728
80024	26727	200	0	0	0	0	0	0	0	0	0	0	26716	2	12	0	16	25	80010	10	80000	10	80000	50	1168843	1	1	49	23651	0	26731	26731	16652	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80059	0	0	0	61	80000	6	1	39	43	0	0	5020	0	0	1	16	2	0	1	3	26732	10	10	4	80000	10	26728	26728	26728	26728	26729
80024	26728	200	0	0	0	0	1	0	0	0	0	1	26713	0	0	0	0	25	80010	10	80000	10	80000	50	1166750	1	1	49	23647	0	26708	26727	16672	3	16708	80010	20	80000	20	80000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80058	0	0	0	60	80040	0	1	39	44	0	0	5020	0	0	1	16	2	0	1	1	26724	14	0	7	80000	10	26709	26728	26732	26732	26742

LDURH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations