Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ASR (register, 32-bit)

Test 1: uops

Code:

  asr w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103582161862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410358061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410358061862251000100010001691601035103572838681000100020001035411110011000473241229371000100010361036103610361036
100410357061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410357061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410358061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410358061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410358061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410358061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036
100410357061862251000100010001691601035103572838681000100020001035411110011000073241229371000100010361036103610361036

Test 2: Latency 1->2

Code:

  asr w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000020071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000010071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387361010010377202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
102041003575052198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000000071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575061986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
1002410035750634986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000364024122994010000100101003610036100361003610036
100241003575061986325100101001010010887841496955100351003586023874010010100202036210035411110021109101001010000064024122994010000100101003610036100361003610036
1002410035750680986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
1002410035750675986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000364024122994010000100101003610036100361003610036
1002410035750149986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  asr w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575061987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750635987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750619987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750668987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886641496955100351003585803872210100102002054810035411110201100991001010010002071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750520987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750441987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003576082986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064034122994010000100101003610036100361003610036
10024100357506609863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100008764024122994010000100101003610036100361003610036
1002410035750504986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003576082986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010010064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035412110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010010364024122994010000100101003610036100361003610036
100241003575082986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000664024122994010000100101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  asr w0, w8, w9
  asr w1, w8, w9
  asr w2, w8, w9
  asr w3, w8, w9
  asr w4, w8, w9
  asr w5, w8, w9
  asr w6, w8, w9
  asr w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413419100182258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111519231338380000801001338713387133871338713387
802041338610035258023980100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111319331338380000801001338713387133871338713387
802041338610035258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111319321338380000801001338713387133871466713387
802041338610035258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005110319231338380000801001338713387133871338713387
80204133861002752580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001000125111319331338380000801001338713387133871338713387
8020413386101390258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111319331338380000801001338713387133871338713387
802041338610135258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111319331338380000801001338713387133871338713387
802041338610035258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111319331338380000801001338713387133871338713387
8020413386101776258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100005111319321338380000801001338713387133871338713387
802041338610035258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100035111319331338380000801001338713387133871338713387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024133861000014425800108001080010400050491029113371133713330333488001080020160020133713911800211091080010100000502410191271336880000800101337213372133721337213372
80024133711000035258001080010800104000504910291133711337133303334880010800201600201337139118002110910800101010005024819981336880000800101337213372133721337213372
8002413371100002252580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010100050218191281336880000800101337213372133721337213372
8002413371100004132580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010000050248196121336880000800101337213372133721337213372
8002413371100004812580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010000050218191281336880000800101337213372133721337213372
800241337110000325258001080010800104000504910291133711337133303334880010800201600201337139118002110910800101020305021819861336880000800101337213372133721337213372
80024133711000010025800108001080010400050491029113371133713330333488001080020160020133713911800211091080010100000502412191281336880000800101337213372133721337213372
800241337110000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010000050226196121336880000800101337213372133721337213372
800241337110000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010000050246196121336880000800101337213372133721337213372
80024133711000035258001080010800104000504910291133711337133303334880010800201600201337139118002110910800101000005021819861336880000800101337213372133721337213372