Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stllrb w0, [x6]
mov x0, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 1e | 1f | 22 | 23 | 24 | 3f | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d cache miss st (a2) | a4 | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1084 | 8 | 0 | 12 | 1 | 1 | 0 | 0 | 1069 | 24 | 25 | 1000 | 1000 | 1000 | 43568 | 1 | 1032 | 1084 | 778 | 3 | 942 | 1000 | 1000 | 2000 | 1085 | 1047 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 19 | 15 | 1000 | 1048 | 1085 | 1085 | 1048 | 1048 |
| 1004 | 1084 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | 1069 | 0 | 25 | 1000 | 1000 | 1000 | 45344 | 0 | 995 | 1085 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1084 | 1084 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 14 | 1000 | 0 | 0 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 0 | 15 | 1000 | 1048 | 1086 | 1085 | 1085 | 1085 |
| 1004 | 1084 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 1032 | 0 | 25 | 1000 | 1000 | 1000 | 45392 | 0 | 1032 | 1084 | 778 | 3 | 905 | 1000 | 1000 | 2000 | 1084 | 1084 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 14 | 1000 | 0 | 0 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 19 | 15 | 1000 | 1048 | 1048 | 1085 | 1085 | 1085 |
| 1004 | 1084 | 8 | 0 | 0 | 1 | 1 | 0 | 0 | 1069 | 20 | 25 | 1000 | 1000 | 1000 | 45344 | 1 | 1032 | 1049 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1085 | 1047 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 14 | 1000 | 0 | 0 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 19 | 15 | 1000 | 1085 | 1085 | 1085 | 1085 | 1048 |
| 1004 | 1084 | 8 | 0 | 0 | 1 | 1 | 0 | 0 | 1069 | 20 | 25 | 1000 | 1000 | 1000 | 45344 | 0 | 1032 | 1084 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1084 | 1084 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 0 | 1000 | 0 | 0 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1081 | 0 | 20 | 15 | 1000 | 1085 | 1085 | 1085 | 1085 | 1085 |
| 1004 | 1084 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 1032 | 20 | 25 | 1000 | 1000 | 1000 | 45344 | 0 | 1032 | 1084 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1084 | 1047 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 0 | 1000 | 0 | 1 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 19 | 15 | 1000 | 1085 | 1085 | 1085 | 1086 | 1085 |
| 1004 | 1047 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | 1032 | 20 | 25 | 1000 | 1000 | 1000 | 45344 | 1 | 1033 | 1092 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1084 | 1084 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 14 | 1000 | 0 | 0 | 0 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 0 | 0 | 1000 | 1048 | 1085 | 1085 | 1085 | 1085 |
| 1004 | 1085 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | 1069 | 20 | 25 | 1000 | 1000 | 1000 | 43568 | 0 | 1032 | 1084 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1084 | 1084 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1081 | 19 | 20 | 0 | 1000 | 1085 | 1085 | 1085 | 1048 | 1048 |
| 1004 | 1084 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 1032 | 20 | 25 | 1000 | 1000 | 1000 | 45392 | 0 | 995 | 1085 | 815 | 3 | 942 | 1000 | 1000 | 2000 | 1084 | 1047 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 14 | 1000 | 0 | 0 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1044 | 19 | 19 | 15 | 1000 | 1085 | 1048 | 1085 | 1048 | 1085 |
| 1004 | 1084 | 9 | 0 | 6 | 1 | 1 | 0 | 0 | 1069 | 0 | 25 | 1000 | 1000 | 1000 | 45344 | 1 | 1032 | 1084 | 815 | 3 | 905 | 1000 | 1000 | 2000 | 1084 | 1047 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 60 | 0 | 1000 | 0 | 0 | 0 | 1000 | 60 | 73 | 1 | 16 | 1 | 1 | 1044 | 0 | 19 | 15 | 1000 | 1048 | 1085 | 1048 | 1085 | 1085 |
Code:
stllrb w0, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0217
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 19 | 1e | 1f | 20 | 22 | 3a | 3e | 3f | 40 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 20206 | 10539 | 78 | 0 | 0 | 0 | 0 | 42 | 14 | 46 | 1 | 20 | 20 | 10208 | 37 | 311 | 25 | 20102 | 10103 | 10000 | 10104 | 10000 | 261403 | 475304 | 1 | 1 | 49 | 7146 | 10362 | 10221 | 7613 | 6 | 7693 | 20104 | 10208 | 10008 | 10208 | 20016 | 10265 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10077 | 8 | 296 | 6 | 74 | 47 | 10070 | 3 | 2 | 41 | 34 | 27 | 10038 | 3 | 414 | 0 | 2 | 1 | 1 | 1 | 1317 | 0 | 16 | 0 | 0 | 10312 | 10002 | 184 | 188 | 81 | 10000 | 10100 | 10203 | 10263 | 10271 | 10241 | 10253 |
| 20204 | 10153 | 77 | 1 | 0 | 0 | 0 | 45 | 9 | 21 | 1 | 19 | 0 | 10135 | 47 | 57 | 25 | 20103 | 10105 | 10000 | 10104 | 10000 | 163973 | 475544 | 1 | 1 | 49 | 7070 | 10127 | 10218 | 7600 | 6 | 7671 | 20104 | 10208 | 10008 | 10208 | 20016 | 10243 | 124 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10116 | 0 | 305 | 5 | 137 | 33 | 10002 | 1 | 0 | 31 | 8 | 17 | 10026 | 8 | 264 | 7 | 0 | 1 | 1 | 1 | 1317 | 0 | 16 | 0 | 0 | 10176 | 10002 | 125 | 116 | 20 | 10000 | 10100 | 10239 | 10152 | 10149 | 10175 | 10190 |
| 20204 | 10218 | 76 | 1 | 0 | 0 | 0 | 18 | 8 | 64 | 1 | 16 | 16 | 10278 | 35 | 101 | 25 | 20103 | 10102 | 10000 | 10104 | 10000 | 322606 | 475352 | 1 | 0 | 49 | 7166 | 10265 | 10296 | 7633 | 6 | 7700 | 20104 | 10208 | 10008 | 10208 | 20016 | 10277 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10033 | 0 | 244 | 8 | 117 | 31 | 10003 | 3 | 0 | 31 | 24 | 11 | 10050 | 10 | 242 | 7 | 1 | 1 | 1 | 1 | 1318 | 0 | 16 | 0 | 0 | 10199 | 10002 | 182 | 131 | 53 | 10000 | 10100 | 10217 | 10222 | 10191 | 10229 | 10266 |
| 20204 | 10191 | 76 | 1 | 1 | 1 | 1 | 6 | 10 | 35 | 1 | 19 | 12 | 10234 | 39 | 148 | 25 | 20104 | 10103 | 10000 | 10104 | 10000 | 231513 | 485912 | 1 | 2 | 49 | 7167 | 10213 | 10227 | 7613 | 6 | 7741 | 20104 | 10208 | 10008 | 10208 | 20016 | 10280 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10057 | 0 | 232 | 7 | 93 | 40 | 10006 | 0 | 0 | 31 | 26 | 3 | 10039 | 9 | 232 | 7 | 2 | 1 | 1 | 1 | 1317 | 0 | 16 | 0 | 0 | 10305 | 10002 | 144 | 131 | 35 | 10000 | 10100 | 10218 | 10251 | 10244 | 10255 | 10217 |
| 20204 | 10243 | 77 | 1 | 1 | 1 | 0 | 24 | 19 | 36 | 0 | 23 | 40 | 10317 | 31 | 81 | 25 | 20104 | 10103 | 10000 | 10100 | 10000 | 233715 | 472808 | 1 | 0 | 49 | 7169 | 10166 | 10201 | 7528 | 3 | 7655 | 20100 | 10200 | 10000 | 10200 | 20000 | 10228 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10049 | 0 | 283 | 5 | 117 | 48 | 10013 | 1 | 0 | 61 | 36 | 8 | 10046 | 11 | 206 | 7 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10168 | 10000 | 165 | 186 | 34 | 10000 | 10100 | 10409 | 10360 | 10273 | 10333 | 10199 |
| 20204 | 10170 | 77 | 0 | 0 | 0 | 0 | 6 | 3 | 28 | 1 | 14 | 0 | 10148 | 37 | 97 | 25 | 20103 | 10101 | 10000 | 10100 | 10000 | 244387 | 475352 | 1 | 1 | 49 | 7162 | 10139 | 10205 | 7526 | 3 | 7663 | 20100 | 10200 | 10000 | 10200 | 20000 | 10249 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10029 | 0 | 177 | 4 | 90 | 39 | 10003 | 1 | 0 | 44 | 42 | 6 | 10036 | 10 | 242 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10171 | 10000 | 92 | 113 | 36 | 10000 | 10100 | 10209 | 10147 | 10249 | 10201 | 10236 |
| 20204 | 10282 | 76 | 1 | 1 | 1 | 0 | 72 | 8 | 39 | 1 | 20 | 24 | 10180 | 31 | 97 | 25 | 20102 | 10101 | 10000 | 10100 | 10000 | 202791 | 471464 | 1 | 1 | 49 | 7087 | 10119 | 10210 | 7541 | 3 | 7693 | 20100 | 10200 | 10000 | 10200 | 20000 | 10287 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10024 | 12 | 350 | 0 | 238 | 30 | 10011 | 3 | 0 | 32 | 0 | 4 | 10013 | 3 | 214 | 0 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10195 | 10000 | 128 | 117 | 24 | 10000 | 10100 | 10168 | 10232 | 10174 | 10175 | 10170 |
| 20204 | 10196 | 76 | 0 | 0 | 0 | 0 | 3 | 4 | 61 | 1 | 20 | 36 | 10253 | 33 | 113 | 25 | 20102 | 10102 | 10000 | 10100 | 10000 | 230453 | 473768 | 1 | 0 | 49 | 7188 | 10247 | 10265 | 7597 | 3 | 7676 | 20100 | 10200 | 10000 | 10200 | 20000 | 10228 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10037 | 0 | 274 | 7 | 106 | 45 | 10003 | 1 | 0 | 45 | 28 | 10 | 10035 | 9 | 242 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10168 | 10000 | 181 | 180 | 107 | 10000 | 10100 | 10173 | 10206 | 10168 | 10227 | 10168 |
| 20204 | 10167 | 78 | 1 | 0 | 1 | 0 | 48 | 8 | 31 | 1 | 17 | 0 | 10213 | 29 | 109 | 25 | 20104 | 10101 | 10000 | 10100 | 10000 | 232797 | 474680 | 1 | 0 | 49 | 7086 | 10169 | 10171 | 7526 | 3 | 7674 | 20100 | 10200 | 10000 | 10200 | 20000 | 10265 | 124 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10041 | 0 | 370 | 7 | 87 | 33 | 10003 | 1 | 0 | 39 | 6 | 3 | 10036 | 10 | 242 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10216 | 10000 | 128 | 106 | 12 | 10000 | 10100 | 10232 | 10197 | 10225 | 10170 | 10204 |
| 20204 | 10205 | 77 | 1 | 1 | 0 | 0 | 6 | 21 | 39 | 1 | 0 | 0 | 10297 | 0 | 204 | 25 | 20104 | 10104 | 10000 | 10100 | 10000 | 97633 | 483560 | 1 | 0 | 49 | 7113 | 10127 | 10170 | 7524 | 3 | 7651 | 20100 | 10200 | 10000 | 10200 | 20000 | 10385 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10027 | 0 | 209 | 6 | 108 | 33 | 10003 | 2 | 0 | 39 | 24 | 8 | 10040 | 10 | 342 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10197 | 10000 | 99 | 110 | 25 | 10000 | 10100 | 10170 | 10225 | 10216 | 10199 | 10192 |
Result (median cycles for code): 1.0181
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 3a | 3e | 3f | 40 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 20026 | 10552 | 78 | 1 | 1 | 1 | 0 | 0 | 6 | 20 | 31 | 1 | 14 | 0 | 10271 | 25 | 126 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 157921 | 475496 | 0 | 49 | 7154 | 10179 | 10211 | 7565 | 3 | 7733 | 20010 | 10020 | 10000 | 10020 | 20000 | 10178 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10064 | 18 | 189 | 7 | 99 | 39 | 10017 | 3 | 0 | 33 | 26 | 30 | 10028 | 16 | 170 | 14 | 4 | 1270 | 3 | 16 | 1 | 1 | 10175 | 10000 | 90 | 88 | 34 | 10000 | 10010 | 10209 | 10202 | 10157 | 10154 | 10183 |
| 20024 | 10183 | 76 | 2 | 2 | 2 | 0 | 0 | 15 | 21 | 35 | 1 | 13 | 0 | 10190 | 29 | 118 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 161612 | 471944 | 0 | 49 | 7076 | 10100 | 10156 | 7638 | 3 | 7713 | 20010 | 10020 | 10000 | 10020 | 20000 | 10327 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10043 | 16 | 170 | 5 | 67 | 27 | 10016 | 2 | 2 | 33 | 22 | 26 | 10023 | 17 | 180 | 14 | 0 | 1270 | 1 | 16 | 1 | 1 | 10181 | 10000 | 111 | 84 | 19 | 10000 | 10010 | 10179 | 10186 | 10231 | 10209 | 10180 |
| 20024 | 10180 | 76 | 2 | 0 | 2 | 0 | 0 | 78 | 17 | 43 | 1 | 11 | 0 | 10169 | 24 | 99 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 229377 | 473000 | 1 | 49 | 7145 | 10150 | 10171 | 7524 | 3 | 7720 | 20010 | 10020 | 10000 | 10020 | 20000 | 10199 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10040 | 8 | 231 | 4 | 80 | 33 | 10009 | 3 | 0 | 33 | 24 | 10 | 10029 | 10 | 232 | 7 | 1 | 1270 | 1 | 16 | 1 | 1 | 10168 | 10000 | 92 | 88 | 13 | 10000 | 10010 | 10180 | 10172 | 10173 | 10172 | 10222 |
| 20024 | 10181 | 76 | 1 | 0 | 0 | 0 | 0 | 0 | 19 | 33 | 1 | 16 | 0 | 10203 | 35 | 157 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 210603 | 473720 | 0 | 49 | 7092 | 10143 | 10153 | 7501 | 3 | 7634 | 20010 | 10020 | 10000 | 10020 | 20000 | 10179 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10029 | 7 | 168 | 6 | 60 | 46 | 10009 | 1 | 2 | 39 | 18 | 23 | 10031 | 11 | 187 | 7 | 0 | 1270 | 1 | 15 | 1 | 2 | 10197 | 10000 | 104 | 119 | 34 | 10000 | 10010 | 10171 | 10175 | 10219 | 10201 | 10149 |
| 20024 | 10170 | 77 | 1 | 1 | 1 | 0 | 0 | 15 | 16 | 33 | 1 | 15 | 0 | 10205 | 27 | 131 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 315859 | 474872 | 0 | 49 | 7043 | 10125 | 10198 | 7548 | 3 | 7626 | 20010 | 10020 | 10000 | 10020 | 20000 | 10193 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10040 | 8 | 146 | 5 | 40 | 37 | 10009 | 2 | 2 | 27 | 16 | 17 | 10032 | 10 | 318 | 7 | 1 | 1270 | 1 | 16 | 2 | 1 | 10167 | 10000 | 93 | 88 | 8 | 10000 | 10010 | 10180 | 10146 | 10149 | 10171 | 10209 |
| 20024 | 10199 | 76 | 1 | 0 | 0 | 0 | 0 | 60 | 10 | 24 | 1 | 18 | 0 | 10209 | 19 | 94 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 327006 | 472664 | 0 | 49 | 7076 | 10130 | 10155 | 7576 | 3 | 7633 | 20010 | 10020 | 10000 | 10020 | 20000 | 10253 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10038 | 26 | 320 | 1 | 78 | 35 | 10016 | 2 | 2 | 33 | 8 | 25 | 10018 | 16 | 212 | 14 | 4 | 1270 | 1 | 15 | 1 | 1 | 10282 | 10000 | 90 | 125 | 13 | 10000 | 10010 | 10223 | 10181 | 10157 | 10159 | 10154 |
| 20024 | 10181 | 76 | 2 | 2 | 1 | 0 | 0 | 30 | 22 | 21 | 1 | 18 | 0 | 10108 | 17 | 61 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 314556 | 472856 | 0 | 49 | 7088 | 10099 | 10170 | 7566 | 3 | 7699 | 20010 | 10020 | 10000 | 10020 | 20000 | 10168 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10052 | 7 | 178 | 3 | 77 | 39 | 10009 | 2 | 1 | 35 | 24 | 20 | 10030 | 9 | 178 | 7 | 1 | 1270 | 1 | 15 | 1 | 1 | 10218 | 10000 | 185 | 180 | 120 | 10000 | 10010 | 10189 | 10175 | 10169 | 10206 | 10193 |
| 20024 | 10218 | 76 | 1 | 0 | 1 | 0 | 0 | 6 | 9 | 31 | 1 | 11 | 28 | 10185 | 25 | 89 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 314861 | 470264 | 0 | 49 | 7089 | 10073 | 10169 | 7548 | 3 | 7650 | 20010 | 10020 | 10000 | 10020 | 20000 | 10143 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10035 | 7 | 190 | 7 | 38 | 37 | 10010 | 2 | 1 | 47 | 24 | 16 | 10023 | 10 | 150 | 7 | 0 | 1270 | 1 | 15 | 1 | 1 | 10197 | 10000 | 90 | 85 | 25 | 10000 | 10010 | 10221 | 10180 | 10172 | 10205 | 10176 |
| 20024 | 10221 | 76 | 1 | 1 | 1 | 0 | 0 | 6 | 13 | 21 | 1 | 16 | 0 | 10164 | 31 | 101 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 287411 | 472568 | 0 | 49 | 7138 | 10127 | 10173 | 7526 | 3 | 7748 | 20010 | 10020 | 10000 | 10020 | 20000 | 10189 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10049 | 7 | 306 | 6 | 73 | 44 | 10010 | 0 | 1 | 37 | 44 | 16 | 10036 | 11 | 542 | 7 | 1 | 1270 | 1 | 16 | 1 | 1 | 10166 | 10000 | 87 | 83 | 28 | 10000 | 10010 | 10196 | 10201 | 10217 | 10154 | 10172 |
| 20024 | 10145 | 76 | 1 | 1 | 1 | 0 | 0 | 12 | 17 | 21 | 1 | 10 | 0 | 10130 | 22 | 60 | 25 | 20011 | 10010 | 10000 | 10010 | 10000 | 319339 | 471368 | 0 | 49 | 7073 | 10127 | 10195 | 7548 | 3 | 7675 | 20010 | 10020 | 10000 | 10020 | 20000 | 10146 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10034 | 7 | 177 | 2 | 133 | 29 | 10009 | 3 | 0 | 33 | 46 | 15 | 10034 | 10 | 178 | 7 | 0 | 1270 | 1 | 15 | 1 | 1 | 10169 | 10000 | 73 | 67 | 10 | 10000 | 10010 | 10169 | 10175 | 10194 | 10204 | 10172 |
Code:
stllrb w0, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0084
| retire uop (01) | cycle (02) | 03 | 1e | 1f | 22 | 23 | 3f | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10205 | 10084 | 76 | 9 | 1 | 0 | 0 | 10069 | 20 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468344 | 1 | 49 | 7004 | 10032 | 10047 | 8653 | 6 | 8780 | 10100 | 200 | 10000 | 200 | 20000 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 60 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 10044 | 0 | 19 | 15 | 10000 | 100 | 10085 | 10085 | 10085 | 10085 | 10085 |
| 10204 | 10084 | 75 | 90 | 1 | 0 | 0 | 10069 | 20 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468338 | 0 | 49 | 6967 | 9995 | 10051 | 8653 | 6 | 8780 | 10100 | 200 | 10000 | 200 | 20000 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 14 | 0 | 10000 | 0 | 0 | 0 | 10000 | 60 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 10081 | 19 | 0 | 15 | 10000 | 100 | 10085 | 10085 | 10085 | 10085 | 10085 |
| 10204 | 10084 | 76 | 30 | 1 | 0 | 0 | 10069 | 0 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 466562 | 0 | 49 | 7004 | 10032 | 10084 | 8616 | 6 | 8780 | 10100 | 200 | 10000 | 200 | 20000 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 14 | 0 | 10000 | 0 | 0 | 3 | 10000 | 60 | 3 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 10081 | 19 | 0 | 0 | 10000 | 100 | 10048 | 10048 | 10085 | 10085 | 10085 |
| 10204 | 10047 | 75 | 105 | 0 | 0 | 0 | 10069 | 0 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468338 | 0 | 49 | 7004 | 10032 | 10084 | 8653 | 19 | 8743 | 10100 | 200 | 10000 | 200 | 20000 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 14 | 0 | 10000 | 0 | 0 | 3 | 10000 | 60 | 1 | 1 | 1 | 722 | 2 | 24 | 0 | 0 | 10081 | 19 | 19 | 15 | 10000 | 100 | 10085 | 10085 | 10111 | 10145 | 10085 |
| 10204 | 10084 | 75 | 48 | 1 | 0 | 0 | 10069 | 20 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 466568 | 0 | 49 | 7004 | 9995 | 10084 | 8672 | 6 | 8788 | 10100 | 200 | 10008 | 200 | 20016 | 10084 | 7918 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 48 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10081 | 0 | 19 | 15 | 10000 | 100 | 10085 | 10085 | 10048 | 10085 | 10048 |
| 10204 | 10047 | 75 | 51 | 1 | 0 | 0 | 10069 | 20 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468344 | 0 | 49 | 6967 | 10032 | 10047 | 8672 | 6 | 8788 | 10100 | 200 | 10008 | 200 | 20016 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 14 | 0 | 10000 | 0 | 0 | 0 | 10000 | 60 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10081 | 19 | 0 | 15 | 10000 | 100 | 10048 | 10048 | 10085 | 10048 | 10048 |
| 10204 | 10084 | 75 | 36 | 1 | 0 | 0 | 10069 | 20 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468344 | 0 | 49 | 7004 | 10032 | 10084 | 8672 | 6 | 8751 | 10100 | 200 | 10008 | 200 | 20016 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 0 | 14 | 0 | 10000 | 0 | 0 | 3 | 10000 | 60 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10081 | 19 | 19 | 15 | 10000 | 100 | 10048 | 10085 | 10048 | 10048 | 10085 |
| 10204 | 10084 | 75 | 48 | 1 | 0 | 0 | 10069 | 0 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468344 | 0 | 49 | 7004 | 9995 | 10084 | 8672 | 6 | 8788 | 10100 | 200 | 10008 | 200 | 20016 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 0 | 14 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10081 | 0 | 0 | 15 | 10000 | 100 | 10085 | 10048 | 10048 | 10085 | 10085 |
| 10204 | 10084 | 75 | 0 | 1 | 0 | 0 | 10069 | 0 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 468344 | 0 | 49 | 7004 | 9995 | 10051 | 8672 | 6 | 8788 | 10100 | 200 | 10008 | 200 | 20500 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 17 | 0 | 10000 | 0 | 0 | 0 | 10000 | 60 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10044 | 0 | 19 | 15 | 10000 | 100 | 10085 | 10048 | 10085 | 10085 | 10085 |
| 10204 | 10084 | 75 | 0 | 0 | 1 | 0 | 10069 | 20 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 466568 | 1 | 49 | 7004 | 9995 | 10047 | 8672 | 6 | 8751 | 10100 | 200 | 10008 | 200 | 20016 | 10084 | 7955 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 60 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 60 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10044 | 19 | 19 | 15 | 10000 | 100 | 10085 | 10085 | 10048 | 10085 | 10085 |
Result (median cycles for code): 1.0088
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 22 | 23 | 3f | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10025 | 10088 | 75 | 1 | 1 | 1 | 1 | 30 | 15 | 1 | 0 | 10073 | 5 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468588 | 0 | 49 | 6975 | 10037 | 10088 | 8658 | 3 | 8819 | 10010 | 20 | 10000 | 20 | 20000 | 10088 | 10055 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 15 | 0 | 5 | 0 | 10014 | 0 | 0 | 14 | 10000 | 14 | 60 | 14 | 1 | 640 | 4 | 16 | 4 | 3 | 10085 | 16 | 15 | 7 | 10000 | 10 | 10056 | 10056 | 10056 | 10089 | 10056 |
| 10024 | 10055 | 76 | 1 | 0 | 0 | 0 | 0 | 15 | 1 | 0 | 10073 | 12 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468588 | 0 | 49 | 7011 | 10003 | 10055 | 8691 | 3 | 8788 | 10010 | 20 | 10000 | 20 | 20000 | 10088 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 15 | 60 | 12 | 1 | 10014 | 0 | 0 | 14 | 10000 | 14 | 0 | 14 | 1 | 640 | 3 | 16 | 4 | 3 | 10086 | 16 | 16 | 0 | 10000 | 10 | 10090 | 10090 | 10089 | 10089 | 10090 |
| 10024 | 10055 | 76 | 1 | 0 | 1 | 1 | 18 | 15 | 1 | 0 | 10074 | 0 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468588 | 0 | 49 | 7009 | 10036 | 10089 | 8692 | 3 | 8818 | 10010 | 20 | 10000 | 20 | 20000 | 10055 | 10055 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10014 | 14 | 60 | 5 | 1 | 10014 | 0 | 0 | 15 | 10000 | 14 | 0 | 14 | 1 | 640 | 4 | 16 | 5 | 4 | 10052 | 0 | 16 | 7 | 10000 | 10 | 10089 | 10090 | 10059 | 10056 | 10056 |
| 10024 | 10055 | 76 | 1 | 1 | 1 | 1 | 0 | 15 | 0 | 0 | 10074 | 20 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468589 | 0 | 49 | 7008 | 10037 | 10055 | 8658 | 3 | 8819 | 10010 | 20 | 10000 | 20 | 20000 | 10089 | 10088 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 16 | 60 | 6 | 0 | 10015 | 0 | 0 | 14 | 10000 | 14 | 60 | 14 | 0 | 640 | 3 | 16 | 3 | 3 | 10086 | 15 | 0 | 7 | 10000 | 10 | 10056 | 10090 | 10090 | 10090 | 10089 |
| 10024 | 10089 | 75 | 1 | 0 | 1 | 0 | 12 | 15 | 1 | 0 | 10040 | 0 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468540 | 0 | 49 | 7008 | 10036 | 10089 | 8692 | 3 | 8822 | 10010 | 20 | 10000 | 20 | 20000 | 10089 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10014 | 15 | 0 | 0 | 2 | 10014 | 0 | 2 | 14 | 10000 | 14 | 60 | 14 | 2 | 640 | 3 | 16 | 4 | 4 | 10086 | 0 | 0 | 12 | 10000 | 10 | 10090 | 10089 | 10090 | 10056 | 10090 |
| 10024 | 10089 | 75 | 1 | 0 | 0 | 1 | 18 | 16 | 1 | 0 | 10073 | 11 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 466956 | 0 | 49 | 7008 | 10036 | 10088 | 8658 | 3 | 8818 | 10010 | 20 | 10000 | 20 | 20000 | 10089 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10014 | 15 | 0 | 6 | 0 | 10014 | 0 | 1 | 14 | 10000 | 14 | 0 | 14 | 1 | 640 | 4 | 16 | 4 | 4 | 10085 | 15 | 0 | 6 | 10000 | 10 | 10056 | 10056 | 10089 | 10089 | 10090 |
| 10024 | 10055 | 75 | 1 | 1 | 1 | 0 | 3 | 14 | 1 | 0 | 10074 | 5 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468589 | 0 | 49 | 7009 | 10003 | 10089 | 8692 | 3 | 8785 | 10010 | 20 | 10000 | 20 | 20000 | 10089 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 14 | 60 | 6 | 0 | 10014 | 0 | 0 | 14 | 10000 | 15 | 60 | 14 | 1 | 640 | 4 | 16 | 4 | 3 | 10086 | 15 | 0 | 11 | 10000 | 10 | 10090 | 10056 | 10089 | 10090 | 10089 |
| 10024 | 10089 | 76 | 1 | 1 | 1 | 1 | 18 | 15 | 0 | 0 | 10074 | 0 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468540 | 0 | 49 | 7009 | 10037 | 10088 | 8692 | 3 | 8819 | 10010 | 20 | 10000 | 20 | 20000 | 10089 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 15 | 60 | 5 | 1 | 10014 | 0 | 2 | 14 | 10000 | 14 | 0 | 14 | 0 | 640 | 3 | 16 | 4 | 3 | 10052 | 16 | 15 | 0 | 10000 | 10 | 10090 | 10089 | 10090 | 10090 | 10056 |
| 10024 | 10089 | 76 | 1 | 0 | 0 | 1 | 18 | 15 | 0 | 0 | 10074 | 11 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 466956 | 0 | 49 | 7008 | 10037 | 10055 | 8692 | 3 | 8819 | 10010 | 20 | 10000 | 20 | 20000 | 10088 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 15 | 60 | 6 | 0 | 10014 | 0 | 1 | 15 | 10000 | 14 | 60 | 14 | 0 | 640 | 4 | 16 | 3 | 4 | 10052 | 16 | 0 | 6 | 10000 | 10 | 10090 | 10090 | 10089 | 10056 | 10059 |
| 10024 | 10058 | 75 | 1 | 1 | 0 | 1 | 3 | 16 | 0 | 0 | 10073 | 11 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 468540 | 0 | 49 | 7009 | 10003 | 10089 | 8691 | 3 | 8819 | 10010 | 20 | 10000 | 20 | 20000 | 10089 | 10089 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10015 | 16 | 60 | 10 | 0 | 10014 | 0 | 1 | 14 | 10000 | 14 | 60 | 14 | 1 | 640 | 3 | 16 | 3 | 4 | 10086 | 15 | 15 | 7 | 10000 | 10 | 10056 | 10056 | 10089 | 10090 | 10090 |