Firestorm: LDRH (register, uxtw) measurements

Code:

  ldrh w0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14838	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	2	16	2	2	386	6	6	2	1000	390	390	390	390	395
1004	394	3	45	0	0	2	379	2	12	18	16	25	1000	1000	1000	15037	1	389	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	6	4	1000	392	395	395	395	395
1004	394	3	45	1	0	2	379	2	12	12	12	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	45	0	0	1	379	2	12	12	12	25	1000	1000	1000	15018	1	394	394	217	3	252	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	10	4	1000	395	390	395	395	395
1004	394	3	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	35	1039	6	1	35	43	73	2	16	2	2	391	10	6	4	1000	395	395	396	395	395
1004	394	3	45	0	0	1	374	2	12	18	11	25	1000	1000	1000	14989	0	389	394	217	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	46	0	0	2	379	2	18	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1039	6	1	35	43	73	2	16	2	2	386	10	6	4	1000	395	395	395	395	395
1004	394	3	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	10	2	1000	395	395	390	393	390
1004	394	2	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15018	0	394	394	216	3	252	1000	1000	2000	394	72	1	1	1001	1000	1000	0	1000	39	1035	0	35	1039	6	1	35	43	73	2	16	2	2	391	10	6	4	1000	395	395	395	395	395
1004	389	3	45	1	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1039	6	1	35	43	73	2	16	2	2	403	10	10	4	1000	395	395	395	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	0	0	0	0	0	0	0	1	0	1	0	0	70310	69735	59706	25	40100	30103	10001	30100	10000	616015	3342062	1	49	66955	0	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	10000	1	1	2610	1	71	1	1	69814	30003	6	6	6	10000	30100	70048	70036	70048	70048	70048
40204	70047	525	0	0	0	1	1	0	0	1	0	1	0	0	70020	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66955	0	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	10000	1	1	2610	1	71	1	1	69831	30003	12	6	0	10000	30100	70048	70048	70036	70048	70049
40204	70047	524	0	0	0	0	0	0	0	1	0	1	0	0	70032	69735	59707	25	40100	30103	10001	30696	10000	616175	3342062	0	49	66967	0	70035	70047	64649	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	2610	1	71	1	1	69875	30003	0	6	6	10000	30100	70048	70051	70036	70048	70036
40204	70035	525	0	0	0	1	0	0	0	0	0	0	1	0	70035	69735	59706	25	40100	30103	10001	30100	10000	616175	3342062	0	49	66967	0	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	1	2610	1	71	1	1	69813	30000	0	0	6	10000	30100	70048	70048	70048	70048	70036
40204	70047	525	0	0	0	0	0	0	0	1	0	0	1	0	70020	69735	59706	25	40100	30103	10001	30100	10000	616015	3342062	0	49	66967	0	70035	70047	64643	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	10000	1	0	2610	1	71	1	1	69863	30003	6	6	6	10000	30100	70048	70048	70048	70048	70036
40204	70047	525	0	0	0	0	0	4	0	1	0	0	1	0	70035	69735	59695	25	40100	30100	10000	30100	10000	616005	3342062	0	49	67340	0	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	10000	1	1	2610	1	71	1	1	69841	30000	6	6	0	10000	30100	70409	70049	70056	70048	70036
40204	70047	525	0	0	0	0	0	0	0	1	0	0	0	0	70032	69764	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	0	70047	70035	64631	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	2610	1	71	1	1	69833	30000	9	0	6	10000	30100	70048	70048	70048	70048	70048
40204	70047	524	0	0	0	0	0	0	0	1	0	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66955	0	70047	70050	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	2	1	10000	0	0	10000	1	1	2610	1	71	1	1	69814	30003	6	6	0	10000	30100	70048	70048	70048	70048	70048
40204	70035	525	0	0	0	0	0	0	0	1	0	0	1	0	70020	69735	59695	25	40104	30103	10001	30100	10000	616175	3342062	1	49	66967	0	70050	70047	64643	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	10000	1	1	2610	1	71	1	1	69840	30003	6	6	6	10000	30100	70048	70051	70048	70036	70036
40204	70035	524	0	0	0	1	0	0	0	1	0	0	1	0	70020	69735	59706	25	40100	30103	10001	30100	10000	616015	3342062	1	49	66967	0	70035	70047	64631	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	3	10000	1	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	0	0	0	1	1	0	0	70032	69743	59706	25	40010	30013	10001	30010	10000	617068	3342062	49	66967	70047	70047	64668	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	1	0	10000	1	1	0	2520	4	71	3	5	69798	30003	6	6	6	10000	30010	70051	70049	70048	70048	70051
40024	70047	524	0	0	0	0	0	1	1	0	0	70020	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	49	66967	70047	70035	64653	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	4	71	4	5	69810	30003	6	6	6	10000	30010	70051	70052	70049	70051	70049
40024	70047	524	0	0	0	0	0	1	0	0	0	70020	69743	59706	25	40010	30013	10001	30010	10000	616952	3342062	49	66970	70047	70047	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	3	10000	1	1	1	2520	4	71	4	6	69813	30003	9	6	6	10000	30010	70054	70036	70052	70048	70048
40024	70050	525	0	0	0	1	0	0	1	0	0	70035	69728	59706	25	40010	30013	10001	30010	10000	616952	3342206	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10012	0	10000	0	0	10000	1	1	0	2520	5	71	3	7	69810	30003	6	0	0	10000	30010	70053	70048	70052	70036	70036
40024	70035	524	0	0	0	0	0	1	0	0	0	70020	69743	59706	25	40014	30013	10000	30010	10000	616982	3342206	49	66967	70035	70035	64665	3	64975	40010	30020	10000	60020	20000	70035	35	2	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	0	0	2520	5	71	4	5	69813	30000	0	6	6	10000	30010	70052	70058	70048	70036	70036
40024	70047	525	0	0	0	0	0	1	1	0	0	70035	69743	59706	25	40014	30013	10001	30010	10000	617068	3341470	49	66955	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	10000	0	0	10000	1	1	0	2520	4	71	5	5	69798	30003	9	9	9	10000	30010	70049	70048	70036	70048	70051
40024	70035	524	0	0	0	0	0	1	0	0	0	70036	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	49	66970	70050	70047	64665	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	4	71	5	4	69900	30003	9	9	9	10000	30010	70081	70082	70052	70050	70048
40024	70047	525	0	0	0	0	0	1	0	0	0	70020	69732	60033	25	40014	30013	10001	30010	10000	616982	3342206	49	66967	70047	70035	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	4	71	6	5	69810	30000	0	0	6	10000	30010	70050	70050	70048	70051	70048
40024	70047	525	0	0	0	0	0	1	1	0	0	70034	69743	59706	25	40014	30013	10001	30010	10000	617036	3342062	49	66955	70035	70047	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10012	1	10000	0	0	10000	1	0	0	2520	4	71	4	6	69813	30003	0	9	0	10000	30010	70052	70048	70036	70048	70048
40024	70035	524	1	0	1	1	0	0	1	0	0	70020	69743	59706	25	40014	30013	10001	30010	10000	616982	3342206	49	66967	70048	70050	64665	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	4	71	3	5	69813	30003	9	9	6	10000	30010	70049	70054	70048	70048	70051

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70050	526	0	0	2	0	1	0	14	16	2248	1056	1	0	0	70049	69781	59709	25	40100	30103	10002	30100	10000	616175	3342206	1	49	66955	70050	70035	64643	3	65025	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	9	6	9	10000	30100	70057	70049	70048	70051	70036
40204	70050	524	1	1	0	0	0	1	0	0	6	0	0	0	0	70032	69781	59695	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66955	70047	70050	64646	3	65045	40100	30397	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69813	30003	6	0	6	10000	30100	70036	70048	70051	70048	70036
40204	70047	524	0	0	0	0	1	1	0	0	0	0	1	0	0	70035	69781	59709	25	40104	30103	10004	30264	10000	616015	3342206	1	49	66970	70053	70035	64631	3	64956	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	1	2610	1	71	1	1	69821	30003	6	0	0	10000	30100	70036	70051	70051	70051	70051
40204	70050	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70032	69764	59695	25	40104	30103	10000	30100	10000	616193	3342206	0	49	66970	70035	70050	64631	3	65037	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69813	30003	6	6	0	10000	30100	70051	70036	70051	70051	70048
40204	70050	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616005	3341470	0	49	63922	70035	70050	64646	3	65055	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69810	30003	0	9	0	10000	30100	70051	70048	70051	70051	70054
40204	70050	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70097	69735	59709	25	40100	30103	10001	30100	10000	616175	3342062	0	49	66955	70050	70050	64646	3	65034	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	6	0	9	10000	30100	70051	70048	70036	70051	70051
40204	70035	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70035	69781	59706	25	40104	30100	10001	30100	10000	616005	3342206	0	49	66967	70050	70047	64646	3	65016	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69813	30003	0	9	0	10000	30100	70048	70051	70048	70051	70051
40204	70035	524	0	1	0	0	0	0	0	0	0	0	0	0	0	70020	69764	59709	25	40128	30103	10001	30100	10000	616005	3342206	0	49	66955	70050	70035	64646	3	65023	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69813	30003	9	0	6	10000	30100	70048	70048	70051	70036	70051
40204	70050	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70032	69735	59706	72	40104	30103	10001	30100	10102	616005	3342206	0	49	66970	70581	70050	64643	3	64985	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70036	70036	70036	70051	70054
40204	70050	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70035	69764	59695	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66955	70035	70050	64643	3	65023	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	9	9	6	10000	30100	70036	70051	70036	70051	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	0	0	0	0	0	0	0	1	0	0	70020	69775	59710	25	40014	30010	10002	30010	10000	616991	3341470	0	1	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	3	71	0	2	2	69798	30000	0	0	10	10000	30010	70036	70036	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	0	0	0	0	70036	69743	59710	25	40014	30013	10001	30010	10000	616991	3341470	0	0	49	66955	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	0	0	0	2520	2	71	0	2	2	69798	30003	10	10	10	10000	30010	70052	70052	70036	70052	70052
40024	70051	525	0	0	0	0	0	0	0	1	0	0	70020	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	1	49	66955	70035	70051	64669	3	64960	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	2	71	0	2	2	69798	30003	0	10	10	10000	30010	70052	70052	70052	70036	70052
40024	70035	525	0	0	0	1	1	0	0	0	0	0	70036	69775	59695	25	40014	30010	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	2520	2	71	0	2	2	69798	30003	10	10	10	10000	30010	70052	70052	70052	70052	70036
40024	70051	524	0	0	0	0	0	0	0	0	1	0	70020	69743	59695	25	40026	30016	10000	30010	10000	616991	3342254	0	0	49	66971	70035	70051	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10000	1	0	0	0	0	2520	2	71	0	2	2	69814	30000	0	0	10	10000	30010	70052	70036	70052	70036	70052
40024	70051	525	0	0	0	0	0	0	0	1	0	0	70036	69743	59710	25	40014	30013	10000	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64653	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	0	0	1	0	0	2520	3	71	0	2	2	69798	30000	13	10	0	10000	30010	70052	70036	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	0	1	0	0	70036	69775	59710	25	40010	30010	10001	30010	10000	616991	3342254	0	0	49	66955	70035	70035	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	0	0	2520	2	71	0	2	2	69798	30003	10	0	10	10000	30010	70052	70052	70036	70053	70036
40024	70035	524	0	0	0	1	1	0	0	1	0	0	70036	69775	59695	25	40014	30013	10001	30010	10000	617068	3342254	0	0	49	66975	70035	70051	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	4	6	10000	1	0	1	0	0	2520	2	71	0	2	3	69814	30003	10	0	10	10000	30010	70056	70052	70415	70039	70222
40024	70038	527	1	0	0	0	0	2	0	33	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342398	0	1	49	66974	70035	70035	64669	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	10000	0	0	1	0	0	2520	2	71	0	2	2	69814	30003	10	10	10	10000	30010	70036	70052	70052	70036	70036
40024	70055	525	0	0	0	0	0	0	0	1	1	0	70036	69775	59710	25	40014	30013	10000	30010	10000	617000	3342254	1	1	49	66971	70051	70035	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	0	0	0	0	0	2520	2	71	0	2	2	69814	30003	0	10	10	10000	30010	70036	70052	70052	70036	70038

Test 4: throughput

Count: 8

Code:

  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]
  ldrh w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	1	0	1	1	0	57	0	1	0	1	26712	0	12	12	16	25	80100	100	80000	100	80016	500	1167303	0	49	23637	26731	26731	16655	6	16679	80115	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80000	6	0	39	0	0	0	1	1	1	5118	16	0	0	26875	10	10	0	80000	100	26728	26879	26997	26728	26819
80204	26727	200	0	0	0	0	1	1	0	0	0	1	0	1	26712	2	12	0	16	25	80100	100	80000	100	80014	500	1166596	0	49	23652	26741	26731	16639	6	16679	80115	200	80024	200	160048	26707	115	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80169	6	0	0	43	0	0	1	1	1	5118	16	0	0	26724	10	0	0	80000	100	26719	26708	26708	26728	26728
80204	26727	200	0	0	0	0	1	1	0	45	0	1	0	0	26692	0	12	0	16	25	80100	100	80000	100	80015	500	1166596	0	49	23656	26707	26707	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	1	0	0	0	0	1	1	1	5118	16	0	0	26708	0	10	4	80000	100	26728	26728	26708	26708	26728
80204	26727	200	0	0	0	0	1	1	4	75	0	1	0	0	26712	0	12	0	0	25	80100	100	80000	100	80014	500	1167303	0	49	23650	26731	26707	16655	6	16679	80114	200	80024	200	160048	26707	77	2	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	39	80039	6	1	0	0	0	0	1	1	1	5118	16	0	0	26724	10	10	0	80000	100	26728	26728	26712	26708	26728
80204	26727	200	0	0	0	0	0	0	0	70	0	0	0	3	26721	0	7	9	0	25	80100	100	80000	100	80016	500	1167377	0	49	23644	26723	26737	16664	6	16688	80116	200	80024	200	160048	26737	85	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	0	80019	0	2	0	24	80000	6	1	59	43	19	2	1	1	1	5141	16	0	0	26715	0	13	5	80000	100	26741	26737	26737	26715	26738
80204	26714	200	1	1	0	1	0	0	0	12	108	1	0	0	26698	2	0	12	18	25	80230	102	80000	100	80014	511	1166596	0	49	23635	26729	26727	16655	6	16659	80114	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	0	0	39	80000	0	1	39	43	0	0	1	1	1	5118	16	1	0	26724	10	0	0	80000	100	26708	26728	26728	26732	26728
80204	26707	200	0	0	0	0	1	1	0	0	0	0	0	1	26692	2	12	0	0	25	80100	100	80000	100	80015	500	1170589	0	49	23717	26751	26740	16663	6	16671	80116	200	80024	200	160048	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	0	80058	0	1	0	63	80038	6	1	19	0	19	2	1	1	1	5118	16	0	0	26711	13	13	0	80000	100	26715	26738	26742	26738	26715
80204	26736	200	1	0	0	1	0	0	0	66	0	0	1	3	26722	3	0	7	0	25	80100	100	80000	100	80015	500	1167628	0	49	23656	26718	26737	16668	6	16688	80114	200	80024	200	160048	26736	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	43	80059	0	1	1	64	80000	0	0	60	43	19	1	1	1	1	5118	16	0	1	26711	0	0	0	80000	100	26738	26715	26737	26715	26715
80204	26736	200	1	0	0	0	0	0	0	66	352	0	0	3	26725	3	7	7	3	125	80100	100	80000	100	80016	500	1167377	0	49	23729	26740	26720	16647	6	16666	80115	200	80024	200	160048	26714	85	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	43	80019	1	0	0	21	80000	6	1	0	43	0	0	1	1	1	5118	16	0	0	26724	0	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	0	0	0	0	0	1	0	26692	2	0	12	16	25	80100	100	80000	100	80015	500	1177116	0	49	23627	26727	26707	16659	6	16679	80115	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	0	80000	0	1	39	43	0	0	1	1	1	5118	16	0	0	26724	10	0	0	80000	100	26708	26728	26728	26708	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26731	200	0	0	0	41	1	0	0	1	26707	2	18	0	12	25	80010	10	80000	10	80000	50	1168843	49	23633	26731	26732	16677	3	16702	80010	20	80000	20	160000	26732	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80035	0	35	80035	6	1	35	43	0	5020	18	16	14	11	26725	6	6	0	80000	10	26725	26732	26732	26723	26733
80024	26713	200	0	0	0	45	1	0	0	2	26707	2	12	18	1	25	80010	10	80000	10	80000	50	1167605	49	23642	26722	26713	16677	3	16711	80010	20	80000	20	160000	26713	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80039	0	39	80018	6	0	18	43	0	5020	11	16	13	11	26710	10	6	0	80000	10	26723	26732	26723	26714	26714
80024	26727	201	0	0	0	45	0	0	0	1	26719	18	18	30	11	25	80010	10	80000	10	80000	50	1166993	49	23642	26722	26713	16871	3	16711	80010	20	80000	20	160000	26731	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80054	0	18	80018	6	0	35	39	0	5020	11	16	11	12	26719	6	6	0	80000	10	26729	26723	26732	26723	26714
80024	26722	200	0	0	0	18	0	0	0	1	26698	2	0	0	16	25	80010	10	80000	10	80000	50	1168843	49	23642	26727	26731	16667	3	16693	80010	20	80000	20	160000	26722	62	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80035	0	18	80018	6	1	35	43	0	5020	11	16	11	11	26710	6	10	4	80000	10	26723	26714	26714	26714	26732
80024	26731	201	0	0	0	25	0	0	0	2	26707	2	18	0	12	25	80010	10	80000	10	80000	50	1167405	49	23652	26713	26713	16667	3	16693	80010	20	80000	20	160000	26722	62	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80035	0	35	80035	6	1	18	43	0	5020	11	16	11	13	26710	6	6	3	80000	10	26729	26714	26729	26732	26723
80024	26732	200	0	0	0	41	1	0	0	1	26707	17	12	0	12	25	80010	10	80000	10	80000	50	1167605	49	23642	26713	26727	16676	3	16693	80010	20	80000	20	160000	26713	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	58	0	80039	0	18	80035	6	1	54	0	0	5020	11	16	13	12	26719	6	0	3	80000	10	26723	26723	26714	26723	26723
80024	26727	201	0	0	0	41	1	0	0	1	26716	2	18	30	17	25	80010	10	80000	10	80000	50	1167292	49	23648	26727	26731	16676	3	16711	80010	20	80000	20	160000	26728	81	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80018	0	35	80018	0	1	39	0	0	5020	11	16	12	12	26710	0	6	0	80000	10	26723	26723	26723	26723	26728
80025	26909	200	0	0	0	41	0	0	0	2	26712	18	0	12	12	25	80010	10	80000	10	80000	50	1166896	49	23662	26735	26726	16659	3	16705	80010	20	80000	20	160000	26719	81	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80035	0	35	80018	0	1	35	39	0	5020	11	16	12	12	26728	6	6	0	80000	10	26723	26729	26732	26729	26714
80024	26727	200	0	0	0	60	0	0	0	1	26712	2	18	18	17	25	80010	10	80000	10	80000	50	1167178	49	23647	26727	26731	16672	3	16712	80010	20	80000	20	160000	26713	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80035	0	39	80035	6	1	18	43	0	5020	12	16	12	12	26719	6	6	4	80000	10	26714	26714	26732	26723	26733
80024	26722	200	0	0	0	41	1	0	0	1	26713	18	12	0	16	25	80010	10	80000	10	80000	50	1168843	49	23642	26722	26713	16672	3	16702	80010	20	80000	20	160000	26713	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	39	0	80039	0	35	80039	0	1	39	43	0	5020	12	16	11	11	26728	6	6	3	80000	10	26723	26723	26733	26733	26723

LDRH (register, uxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations