Firestorm: XPACD measurements

Code:

  xpacd x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	66	0	0	0	84	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	1	1	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	104	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7144	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	105	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	4	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	12	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	18	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  xpacd x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	616	1	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	4	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	4	0	2	79	1	0	69796	10100	10100	70072	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	1	0	0	0	103	59824	25	10200	10200	10200	1808330	1	4	98	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	1	0	0	710	4	0	1	79	1	1	69908	10100	10100	70030	70030	70030	70030	70030
10205	70029	620	0	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	4	49	66949	0	70029	70029	68480	3	68674	10230	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	4	0	1	79	1	1	69796	10104	10100	70030	70030	70030	70030	70030
10204	70029	621	1	0	0	0	0	0	0	0	0	773	59824	25	10200	10200	10229	1808330	1	4	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70069	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	4	0	1	79	1	1	69796	10100	10100	70030	70030	70069	70787	71248
10204	70029	657	0	0	0	0	0	0	528	0	0	61	59824	25	10204	10200	10200	1808330	1	4	49	66988	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	0	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	1	128	59824	25	10200	10200	10200	1808739	1	0	49	66949	0	70068	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	0	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	4	12	0	0	176	59824	25	10200	10200	10200	1808330	1	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	0	0	1	79	1	1	69796	10100	10100	70030	70030	70070	70030	70030
10204	70029	617	0	0	0	0	5	0	144	0	0	61	59824	25	10200	10200	10200	1808330	1	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	2	0	0	0	0	710	0	0	2	79	1	1	69796	10100	10100	70030	70069	70030	70030	70030
10204	70029	619	0	0	0	0	0	0	0	0	0	571	59824	25	10200	10200	10316	1808330	1	0	49	66949	0	70029	70029	68480	19	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	0	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	0	726	59824	110	10200	10200	10200	1808330	1	0	49	66949	0	70029	70029	68520	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	0	0	1	79	1	1	69796	10100	10100	70030	70030	70069	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	617	0	0	0	0	0	0	33	2200	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	655	0	0	0	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70068	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	0	71	59815	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	63908	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	4	69915	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	3	0	0	640	2	79	2	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	1	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70069	70030
10024	70029	620	0	0	0	0	0	0	0	0	0	5802	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	1665	0	0	654	2	79	2	2	69805	10010	10010	70030	70059	70030	70069	70030
10024	70029	617	0	0	0	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70058	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  xpacd x0
  xpacd x1
  xpacd x2
  xpacd x3
  xpacd x4
  xpacd x5
  xpacd x6
  xpacd x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	1f	3f	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	699	0	0	0	35	0	25	80200	80200	80200	401000	1	49	76955	80080	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	5120	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	701	0	12	0	35	0	25	80200	80200	80200	401000	1	49	73920	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	35	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	1192	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	5110	2	17	2	2	80025	80100	80100	80036	80036	80036	80036	80171
80204	80035	701	0	0	0	35	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	1	5110	2	25	2	2	80025	80120	80100	80036	80036	80036	80036	80036
80204	80035	702	0	12	0	35	0	25	80200	80200	80200	401000	1	49	77136	80079	80126	69966	8	70149	80244	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80081	80036	80036
80204	80035	702	0	0	0	35	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	0	5110	2	25	3	2	80025	80100	80100	80036	80036	80036	80036	80036
80205	80035	743	0	0	0	134	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80256	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80072	80036	80036	80036	80036
80204	80035	699	0	0	0	35	0	110	80200	80221	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	35	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80073	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80051	698	0	0	0	0	0	0	249	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	3	0	5020	5	25	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	713	0	0	0	0	0	0	948	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	2	0	0	0	0	0	5020	4	25	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	694	0	0	0	0	0	0	969	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	2	25	2	4	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	915	0	0	35	25	80020	80020	80020	400100	0	49	76955	80080	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	3	0	5020	2	25	2	4	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	531	0	0	415	25	80020	80020	80020	400207	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80072	164	1	1	80021	10	9	80010	0	0	1	0	0	0	5020	4	25	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	749	0	0	0	0	1	0	843	0	0	63	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	4	25	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	749	0	0	0	0	0	0	1221	0	0	700	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	4	33	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	697	0	0	0	0	0	0	1269	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	4	25	2	4	80024	80031	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	456	88	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	4	25	4	4	80024	80010	80010	80036	80080	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	951	0	0	728	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	4	25	5	4	80024	80010	80010	80036	80036	80036	80036	80036

XPACD

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations