Firestorm: MSR (APRR) measurements

Code:

  msr s3_6_c15_c1_5, x0

Initialization

  mrs x0, s3_6_c15_c1_5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	1027	8	0	1012	25	1	1027	1075	865	3	875	1027	1027	1	1	1001	1	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	7	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	3	3	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	7	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028
1004	1027	8	0	1012	25	1	1027	1027	865	3	875	1027	1027	1	1	1001	0	0	73	1	25	1	1	1024	1028	1028	1028	1028	1028

Code:

  msr s3_6_c15_c1_5, x0

Initialization

  mrs x0, s3_6_c15_c1_5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1127

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int retires (ef)	f5	f6	f7	f8	fd
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	5	0	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	1	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	1	3	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	12	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	12	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	12	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	30	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	66	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	21	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	15	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128
10204	11127	86	0	11112	34	100	100	100	500	0	49	8047	11127	11127	9815	7	9828	100	200	200	11127	8870	1	1	10201	100	99	100	100	100	0	15	1	1	1	719	16	11124	100	11128	11128	11128	11128	11128

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0137

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
10024	10137	78	0	0	0	0	0	0	10122	26	10	10	10	50	1	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	48	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	78	0	0	0	0	0	0	10122	26	10	10	10	50	1	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	0	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	78	0	0	0	0	0	0	10122	26	10	10	10	50	1	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	1	3	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	79	0	0	0	0	88	0	10122	26	10	10	10	50	0	49	7057	10137	10137	8833	3	8892	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	1	6	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	79	0	0	0	0	0	0	10122	26	10	10	10	50	1	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	0	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	79	0	0	0	0	0	0	10122	26	10	10	10	50	1	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10022	10	9	10	10	10	0	0	0	3	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	78	0	0	0	0	0	0	10122	26	10	10	10	50	0	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	3	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	78	0	0	0	6	0	0	10122	26	10	10	10	50	0	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	0	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	79	0	0	0	0	0	0	10122	26	10	10	10	50	0	49	7057	10137	10137	8833	3	8892	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	0	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138
10024	10137	78	0	0	0	0	0	0	10122	26	10	10	10	50	0	49	7057	10137	10137	8833	3	8855	10	20	20	10137	10137	1	1	10021	10	9	10	10	10	0	0	1	0	0	640	2	28	2	2	10134	10	10138	10138	10138	10138	10138

MSR (APRR)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations