Firestorm: PACIZB measurements

Code:

  pacizb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	0	0	0	12	0	125	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	2	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	96	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	191	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	1	0	0	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	63	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	3	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	141	0	126	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	2	0	0	0	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	3	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	2	1	6789	1000	0	0	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  pacizb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	619	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	1	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70072	70030	70030	70030
10204	70029	622	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	3	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	652	0	66	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10248	10200	70029	912	1	1	10201	100	99	10100	0	1	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	9	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	5	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	618	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	3	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	2	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	61	59824	47	10203	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	649	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	1	0	0	710	0	2	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	618	0	536	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	2	42	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	619	0	0	0	0	0	0	0	0	0	84	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	3	0	640	4	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	652	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	618	0	0	0	0	0	0	0	0	0	156	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	8	68622	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	3	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	103	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	1	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70185	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	642	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	651	0	0	0	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	63903	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70190	70070	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  pacizb x0
  pacizb x1
  pacizb x2
  pacizb x3
  pacizb x4
  pacizb x5
  pacizb x6
  pacizb x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	699	0	0	0	0	150	0	0	77	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	2	0	0	0	0	324	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	9	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	35	47	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	6	0	0	5110	2	25	2	2	80025	80100	80100	80127	80036	80036	80036	80036
80204	80035	695	0	0	0	0	3	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	1	0	0	0	12	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80233	80035	164	1	1	80201	100	99	80100	3	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80082	80036	80036	80036	80036
80204	80035	696	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	2	80058	80100	80100	80036	80036	80036	80036	80036
80204	80035	750	0	0	0	0	0	0	0	77	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	2	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80082	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	700	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80081	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	1	0	0	0	0	0	520	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	98	25	80200	80200	80200	401000	1	49	77001	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	1	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80041	699	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	14	0	5020	0	0	0	6	25	6	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	0	217	25	80020	80020	80020	400322	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	1	0	5020	0	0	0	6	25	6	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	746	0	0	0	0	0	0	0	63	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5020	0	0	0	3	25	3	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	27	0	300	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5020	0	0	0	3	25	3	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	706	0	0	0	0	0	0	0	61	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5467	0	0	0	7	315	15	8	81247	80725	0	80010	81620	81575	81347	81760	81713
80024	81579	709	0	0	0	0	0	0	0	203	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5020	0	0	0	6	25	6	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	40	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5020	0	0	0	3	25	3	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	12	0	56	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5020	0	0	0	6	25	7	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	12	0	1015	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	1	3	5020	0	0	0	3	25	3	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	703	0	0	0	0	0	27	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	0	80010	0	0	5020	0	0	0	3	25	3	6	80024	80010	2	80010	80036	80036	80036	80036	80036

PACIZB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations