Firestorm: UDIV (slow, 64-bit) measurements

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	12	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	463	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	3	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	61	950	25	1000	1000	1000	53725	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	110035	824	0	0	0	30	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110074	105815	3	3	106243	30100	30200	60200	110064	210	1	1	30201	100	99	100	30100	100	0	0	0	88	0	0	0	0	1910	2	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	1	16	1	0	109666	30000	30100	110036	110036	110036	110213	110036
30204	110035	825	0	0	0	0	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	82	100940	25	30100	30100	30100	10432628	49	106955	3	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30205	110035	824	0	0	0	0	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	0	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	825	0	0	0	0	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	1	0	61	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	61	100940	25	30100	30110	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	825	0	0	0	0	726	100940	25	30100	30100	30100	10432628	49	106955	0	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
30024	110035	824	0	0	0	0	0	0	0	61	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	3	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	61	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	3	0	0	1890	2	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	825	0	0	0	0	0	0	0	61	101155	25	30010	30010	30010	10434631	49	106955	110035	110076	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	2	109677	30000	0	30010	110036	110066	110036	110036	110036
30024	110035	824	0	0	0	0	90	0	0	61	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	726	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	3	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	61	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	156	0	0	1890	2	16	2	8	110285	30000	0	30010	111194	111195	111148	111233	111201
30024	111185	833	1	1	21	25	3168	1232	1	14478	100994	532	30156	30165	32622	10441173	49	107760	111110	111192	106038	112	106824	32519	33033	65854	110790	210	19	1	30021	10	9	10	30010	10	0	0	3	2	35986	0	0	1890	2	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	536	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105872	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	61	101155	25	30010	30010	30010	10434631	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	3	2	109677	30000	0	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	747	101155	25	30010	30010	30010	10464318	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	65	0	0	0	1890	2	16	2	2	109677	30000	0	30010	110036	110036	110036	110036	110036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	0	49	103915	0	110035	110035	105824	7	106239	30100	30208	60216	110035	210	1	1	30201	100	99	100	30100	100	0	0	1	1	1	1918	0	16	0	0	109680	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105824	6	106238	30100	30208	60216	110035	210	1	1	30201	100	99	100	30100	100	4	9	1	1	1	1917	0	16	0	0	109680	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	747	100940	25	30100	30100	30100	10432628	0	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	251	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	6	3	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	726	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1937	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	16	1	1	109773	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	0	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	110035	824	0	0	0	0	0	0	30	0	892	101155	110019	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	1	1	0	0	0	0	0	0	338	101155	0	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	1	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	6	0	168	101155	0	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	183	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	0	252	101155	0	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	0	166	101155	0	25	30010	30010	30010	10434631	1	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110057
30024	110035	825	0	0	0	0	0	0	0	0	359	101155	0	25	30010	30010	30010	10434631	1	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	0	61	101155	0	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	0	61	101155	0	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30025	110035	824	0	0	0	0	0	0	0	0	340	101155	0	25	30010	30010	30010	10434631	0	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	4	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	0	0	0	0	0	0	250	101155	0	25	30010	30010	30010	10434631	1	49	106955	0	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	4	16	2	4	109677	30000	30010	110036	110036	110036	110036	110036

Test 4: throughput

Count: 8

Code:

  udiv x0, x8, x9
  udiv x1, x8, x9
  udiv x2, x8, x9
  udiv x3, x8, x9
  udiv x4, x8, x9
  udiv x5, x8, x9
  udiv x6, x8, x9
  udiv x7, x8, x9

Initialization

  mov x8, #0xffffffffffffffff
  mov x9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160040	1198	0	30	61	79950	25	80100	80100	80100	4399225	1	98	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	0	726	79950	25	80100	80100	80100	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	1	0	0	5110	0	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	9	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	0	0	726	79950	25	80100	80100	80100	4399225	0	49	156960	160040	160040	149901	18	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	2	186	0	5110	1	16	2	2	160019	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	0	61	79950	25	80100	80100	80100	4399225	1	49	157010	160077	160040	149901	21	150034	80275	80308	160200	160040	261	1	1	80201	100	99	100	80100	100	1	3	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	1	0	726	79950	25	80100	80100	80100	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	0	0	61	79950	25	80100	80100	80139	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	3	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	0	726	79950	25	80100	80100	80100	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	174	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	17	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	21	726	79950	25	80100	80100	80100	4399225	1	49	156960	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160040	1198	0	0	0	0	0	0	0	0	61	79950	45	80010	80040	80010	4398954	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80076	160218	160040	261	1	1	80021	10	9	10	80010	10	1	0	5020	4	16	0	4	3	159980	80000	80010	160041	160041	160041	160041	160041
80024	160242	1198	0	1	1	2	8	12	0	0	103	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	3	0	5020	3	16	0	4	4	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80023	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	2	1	80021	10	9	10	80010	10	0	0	5020	5	32	0	4	4	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	0	0	0	0	0	648	0	0	61	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	5020	4	16	0	4	3	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	5020	3	16	0	4	4	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	0	0	0	0	0	0	0	0	726	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160080	261	1	1	80021	10	9	10	80010	10	0	0	5020	4	16	0	4	4	159980	80013	80010	160041	160041	160041	160041	160041
80024	160040	1198	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	1	0	5020	4	16	0	3	4	159980	80000	80010	160041	160041	160041	160041	160041
80025	160040	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	5020	4	16	0	3	4	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160074	160040	261	1	1	80021	10	9	10	80010	10	0	0	5020	4	16	0	3	4	159980	80000	80010	160091	160041	160041	160041	160142
80024	160091	1199	0	0	0	0	0	0	0	0	326	79950	25	80010	80010	80010	4398775	0	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	5020	4	16	0	4	4	159980	80000	80010	160041	160041	160041	160041	160041

UDIV (slow, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations