Firestorm: LDRSB (post-index, 64-bit) measurements

Code:

  ldrsb x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	20	22	23	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	7	0	0	0	0	46	20	1	0	0	0	0	1025	15	0	3	0	18	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1013	0	0	41	1028	4	0	28	0	8	14	1016	48	7	11	24	0	0	73	2	16	1	1	1037	1000	28	35	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	46	14	1	0	0	0	20	1025	0	0	4	3	18	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	0	1	48	1010	3	0	16	0	12	9	1012	30	4	14	48	0	0	73	1	16	1	1	1037	1000	32	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	1	0	48	0	1	0	0	0	4	1025	0	0	6	0	22	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1013	0	0	51	1024	3	0	13	0	12	17	1010	30	6	8	56	0	23	73	1	16	1	1	1037	1000	33	31	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	48	16	1	0	0	0	0	1025	12	0	2	0	9	25	2000	1000	1000	1000	1000	52852	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1014	0	0	42	1021	0	0	14	0	14	10	1023	24	5	12	48	0	0	73	1	16	1	1	1037	1000	32	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	1	0	0	62	14	0	0	0	0	0	1025	0	0	0	0	16	25	2000	1000	1000	1000	1000	52844	45836	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	45	1	1	1001	1000	1000	0	1000	0	1	42	1020	2	0	12	0	10	12	1044	24	5	8	32	0	0	73	1	16	1	1	1037	1000	34	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	32	32	1	0	0	0	0	1025	11	0	0	0	17	25	2000	1000	1000	1000	1000	52852	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1015	0	0	57	1010	0	0	0	0	6	11	1012	42	6	15	48	0	0	73	1	16	1	1	1037	1000	44	27	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	56	22	0	0	0	0	0	1025	11	0	2	2	10	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	48	1014	0	0	0	0	0	10	1012	24	5	12	40	0	9	73	1	16	1	1	1037	1000	32	30	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	32	10	0	0	1	0	4	1025	9	1	0	2	17	25	2000	1000	1000	1000	1000	52852	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1015	0	1	33	1024	4	0	12	0	0	12	1041	36	5	12	48	0	0	73	1	16	1	1	1037	1000	28	30	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	54	17	1	0	1	3	4	1025	11	0	1	0	18	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	0	0	41	1038	2	0	12	0	4	10	1026	30	6	14	56	0	0	73	1	16	1	1	1037	1000	36	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	1	0	0	40	0	0	0	0	0	20	1025	10	2	0	2	15	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1015	0	1	68	1025	3	0	15	0	8	15	1037	48	6	16	48	0	0	73	1	16	1	1	1021	1000	34	30	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1897

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	1f	20	22	29	3a	3e	3f	40	43	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72189	539	1	0	0	0	0	469	0	822	1	648	3	112	71810	780	0	71665	25	50760	40572	10127	40100	10000	614462	2725044	1	49	68619	0	71737	71731	65461	3	65533	50100	40200	10000	70200	10000	71843	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10934	2	159	500	10633	260	11	905	46	26	10908	125	2	128	2	0	3	2610	2	58	1	1	71603	40536	1066	1106	1094	10000	40100	71824	71681	71960	72037	72134
50204	71896	538	2	0	1	0	0	424	0	865	1	736	2	136	71690	802	0	71581	25	50820	40600	10132	40100	10000	614069	2718056	1	49	68852	0	71958	71792	65326	3	65613	50100	40200	10000	70200	10000	71885	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10879	4	159	491	10651	282	12	928	76	38	10956	123	2	134	2	3	9	2610	1	58	1	1	71680	40452	1121	1043	1070	10000	40100	71750	71850	71907	71596	71992
50204	71989	537	2	0	0	0	0	428	0	859	1	704	2	140	71805	790	0	71766	25	50750	40672	10127	40100	10000	615675	2726047	1	49	68859	0	71742	72125	65377	3	65656	50100	40538	10000	70200	10000	72054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10932	4	155	484	10644	261	16	959	68	20	10928	129	2	128	2	0	3	2651	1	58	1	1	71567	40512	1040	1099	1102	10000	40100	71809	72040	71788	71823	71868
50204	71658	538	2	0	1	0	0	401	0	817	1	464	2	144	71886	874	0	71519	25	50700	40624	10121	40100	10000	616084	2729886	1	49	68842	0	71897	71970	65557	3	65652	50100	40200	10000	70200	10000	71811	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10907	2	163	549	10667	256	11	896	136	130	10986	135	2	108	2	3	10	2610	1	58	1	1	71820	40516	1022	1117	1015	10000	40100	72025	71768	71822	71898	71869
50204	71895	540	2	0	2	0	1	439	0	856	1	728	2	120	71890	815	0	71496	25	50785	40572	10131	40100	10000	615780	2723496	0	49	68792	0	71986	72019	65269	3	65730	50100	40200	10000	70200	10000	72055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10895	2	161	475	10627	268	11	946	50	32	10897	132	2	133	2	4	5	2610	1	57	1	1	71578	40504	1055	890	1087	10000	40100	71935	71775	71815	71862	71783
50204	71929	539	2	0	2	0	0	454	0	851	1	712	2	116	72065	826	0	71615	25	50725	40612	10141	40100	10000	614696	2720191	1	49	68710	0	71832	71737	65422	3	65687	50100	40200	10000	70200	10000	71897	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10881	2	137	475	10616	236	10	929	48	32	10906	123	2	118	2	5	10	2610	1	58	1	1	71596	40496	985	1005	1095	10000	40100	71682	71879	72027	71961	71815
50204	71885	538	2	0	2	0	1	475	0	821	1	768	2	96	71909	816	0	71522	25	50665	40564	10136	40100	10000	616081	2730155	1	49	68907	0	71808	71900	65453	3	65551	50100	40200	10000	70200	10000	71847	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10906	2	127	502	10633	259	11	926	36	35	10953	140	2	123	2	0	9	2610	1	58	1	1	71796	40444	1097	1076	1107	10000	40100	71985	71795	71804	71899	71819
50204	71759	538	2	0	2	0	1	444	0	815	1	704	2	132	71972	789	0	71720	25	50690	40640	10127	40100	10000	612612	2717599	1	49	68921	0	71957	71922	65325	3	65598	50100	40200	10000	70200	10000	71909	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10903	2	157	514	10634	271	11	944	54	32	10962	123	2	136	2	2	3	2610	1	58	1	1	71763	40508	1145	1147	1150	10000	40100	71884	71947	71899	72011	72016
50204	71866	537	2	0	1	0	0	437	0	815	1	728	2	112	71822	805	0	71715	25	50780	40604	10127	40100	10000	614553	2726072	0	49	68868	3	71736	72039	65327	3	65662	50100	40200	10000	70200	10000	71762	76	1	1	40201	100	99	100	10000	30100	10000	0	100	10914	2	158	509	10623	266	15	908	82	29	10898	120	2	131	2	0	9	2610	1	58	1	1	71638	40552	1184	1148	1057	10000	40100	71685	71980	71908	71793	71982
50204	71993	539	2	0	0	0	1	399	0	817	1	712	2	124	72041	843	0	71702	25	50675	40604	10124	40100	10000	614511	2733486	1	49	68890	0	71940	72097	65384	3	65512	50100	40200	10000	70200	10000	71990	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10887	2	159	487	10635	253	12	886	78	26	10930	137	2	110	2	3	11	2610	1	58	1	1	71570	40504	1088	1095	1036	10000	40100	72233	71908	71908	71705	71780

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.2069

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	18	1e	1f	20	22	29	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72289	539	0	0	0	467	0	868	1	768	140	72070	821	6	4	71635	25	50755	40582	10116	40010	10000	613866	2731626	0	49	68855	72049	71893	65401	3	65607	50010	40020	10000	70020	10000	72144	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10952	0	161	517	10664	274	21	955	46	58	10960	127	6	132	0	3	0	2520	0	5	85	0	14	14	71856	40588	1187	1169	1163	10000	40010	72171	72081	72119	72206	72189
50024	72095	540	0	0	0	438	0	867	1	632	136	72106	850	7	2	71782	25	50775	40562	10150	40010	10000	614773	2728844	0	49	68884	72177	72085	65669	3	65704	50010	40020	10000	70020	10000	72094	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10951	0	147	519	10684	284	19	962	72	29	10990	141	9	138	0	10	0	2520	0	5	85	0	5	14	71858	40540	1092	1113	1091	10000	40010	71956	71844	71971	72104	72000
50024	72015	538	0	0	0	491	0	859	1	744	140	72098	849	6	3	71625	25	50760	40538	10150	40010	10000	615259	2730058	0	49	69134	72053	72186	65473	3	65608	50010	40020	10000	70020	10000	72123	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10955	0	157	553	10662	292	17	970	74	52	10954	146	7	140	0	7	0	2520	0	11	85	0	4	14	71997	40573	968	1110	1012	10000	40010	72052	71971	72215	72022	72102
50024	72086	540	0	0	0	503	0	875	1	720	144	71947	845	5	2	71884	25	50690	40602	10133	40010	10000	613972	2725136	0	49	68936	71831	72229	65577	3	65669	50010	40020	10000	70020	10000	72098	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10950	0	152	539	10667	278	19	950	48	46	10969	134	12	142	3	3	0	2520	0	14	101	0	12	12	71843	40616	1101	1166	1144	10000	40010	72053	72165	72275	71979	72018
50024	71930	539	0	0	0	436	0	876	1	752	176	72122	838	6	4	71925	25	50740	40598	10150	40010	10000	613820	2733065	0	49	68805	72069	71952	65719	3	65689	50010	40020	10000	70020	10000	72142	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10970	0	156	509	10704	276	22	979	74	50	10954	145	9	145	0	9	0	2520	0	14	85	0	5	14	71907	40580	1221	1219	1143	10000	40010	72163	72044	72007	71997	71907
50024	72111	540	0	0	0	433	0	869	1	760	152	72064	843	8	6	71739	25	50670	40598	10131	40010	10000	616267	2738195	0	49	69040	72178	72015	65508	3	65744	50010	40020	10000	70020	10000	72142	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10980	0	152	516	10692	283	19	986	48	54	10952	138	5	143	0	7	0	2520	0	14	85	0	14	14	71933	40632	1158	1103	1180	10000	40010	72049	71989	72042	72201	71962
50024	72121	539	0	0	0	516	0	898	1	768	140	72048	845	9	2	71780	25	50730	40566	10135	40010	10000	614852	2734050	0	49	68993	71936	71966	65546	3	65619	50010	40020	10000	70020	10000	72018	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10953	0	144	532	10677	280	21	962	82	59	10979	141	6	127	3	3	0	2520	0	6	85	0	6	14	72137	40592	1114	1099	1076	10000	40010	72233	72050	71866	72006	72176
50024	72044	540	0	0	0	448	0	872	1	752	112	72123	845	4	6	71950	25	50760	40606	10141	40010	10000	613792	2730416	0	49	69060	72130	71901	65404	3	65767	50010	40020	10000	70020	10000	72295	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10963	0	146	528	10658	280	18	959	76	57	10954	149	6	144	0	3	0	2520	0	14	85	0	14	4	71906	40576	1100	1186	1206	10000	40010	72104	71825	72064	72154	71901
50024	71923	540	0	0	0	466	0	846	1	728	136	71932	827	7	2	71712	25	50690	40582	10159	40010	10000	613597	2736301	0	49	69039	72052	71991	65559	3	65669	50010	40020	10000	70020	10041	72121	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10964	0	151	484	10683	291	21	972	38	44	10964	141	5	142	0	3	0	2520	0	14	66	0	5	14	72109	40608	1179	1170	1188	10000	40010	72415	72114	72058	72055	72185
50024	72131	539	0	0	0	536	0	853	1	752	112	72255	841	6	3	71801	25	50745	40530	10156	40010	10000	614562	2727918	0	49	68967	72138	72017	65474	3	65748	50010	40020	10000	70020	10000	72020	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10956	0	146	535	10684	273	17	958	76	43	10959	133	9	162	15	3	0	2520	0	5	85	0	14	5	71967	40536	1123	1184	1157	10000	40010	72313	72062	72394	72048	72010

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6], #8
  ldrsb x0, [x7], #8
  ldrsb x0, [x8], #8
  ldrsb x0, [x9], #8
  ldrsb x0, [x10], #8
  ldrsb x0, [x11], #8
  ldrsb x0, [x12], #8
  ldrsb x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3670

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29658	220	2	0	2	0	0	2	6883	783	1	728	105	96	29114	782	415	1863	1631	2059	25	160463	80518	80000	80100	80169	400731	1303678	0	58	49	26280	29375	29312	9282	3	9199	160100	80200	80000	80200	80000	29206	35	1	1	80201	100	99	27	100	80000	100	80000	100	80941	37	387	5312	0	85809	681	12	896	28	4606	85814	722	117	5303	4566	37	0	0	5110	1	16	1	1	29423	36	80057	478	508	111	80000	80100	29574	29399	29228	29513	29226
160204	29524	221	2	2	0	1	0	0	7207	814	1	736	99	52	29464	791	350	1825	1776	2186	25	160160	80168	80000	80100	80000	400774	1286905	1	63	49	26142	29295	29288	9132	3	9167	160100	80200	80000	80200	80000	29328	35	1	1	80201	100	99	39	100	80000	100	80000	100	80922	27	444	5396	0	85199	653	17	885	22	4702	85558	673	106	4512	4706	36	2	3	5110	1	17	1	1	29379	23	80065	524	539	107	80000	80100	29328	29740	29410	29281	29488
160204	29605	218	2	2	2	0	0	0	6584	784	1	688	93	100	29109	756	373	2057	1671	2014	25	160157	80164	80000	80100	80000	400724	1295816	1	59	49	26191	29173	29578	9473	3	9164	160100	80200	80000	80200	80000	29363	35	1	1	80202	100	99	18	100	80000	100	80000	100	80896	36	394	5642	0	84682	649	12	902	30	5214	85769	820	121	5161	5177	38	0	7	5129	1	16	1	1	29375	37	80051	500	504	91	80000	80100	29488	29590	29722	29392	29457
160204	29428	218	2	0	1	0	0	0	7063	786	1	744	91	148	29254	764	362	1754	1836	2174	25	160162	80158	80000	80100	80000	400776	1299455	0	66	49	26218	29456	29251	9278	3	9383	160100	80200	80000	80200	80000	29288	35	1	1	80201	100	99	25	100	80000	100	80000	100	80909	37	405	5505	0	84878	626	9	854	72	4697	85837	744	110	4362	4973	37	1	5	5110	1	16	1	1	29373	36	80055	544	548	106	80000	80100	29228	29689	29418	29432	29300
160204	29329	221	2	1	2	1	0	0	7254	799	1	568	96	116	29263	750	432	1721	1941	2142	25	160170	80157	80000	80100	80000	400775	1293181	0	64	49	26192	29255	29323	9336	3	9100	160100	80200	80000	80200	80000	29314	35	1	1	80201	100	99	20	100	80000	100	80000	100	80913	36	451	5327	0	85057	688	12	869	36	4896	85629	690	137	4706	4910	37	4	2	5110	1	16	1	1	29536	27	80066	571	618	99	80000	80100	29356	29414	29169	29332	29367
160204	29360	221	2	2	0	0	0	0	6878	845	1	720	101	124	29299	757	342	1912	1668	2015	25	160167	80164	80000	80100	80000	400756	1296991	1	72	49	26385	29353	29374	9364	3	9364	160100	80200	80000	80200	80000	29432	35	1	1	80201	100	99	35	100	80000	100	80000	100	80907	36	402	5993	27	85648	648	8	906	34	6111	85764	740	135	5028	4190	37	0	6	5110	1	16	1	1	29673	25	80054	545	538	113	80000	80100	29423	29505	29318	29180	29399
160204	29935	224	2	0	1	0	0	2	6787	805	1	720	105	108	29402	798	304	1859	1784	2247	59	160449	80339	80223	80265	80169	401606	1294173	0	56	49	26317	29226	29502	9282	3	9232	160100	80200	80000	80200	80000	29305	35	1	1	80201	100	99	29	100	80000	100	80000	100	80943	35	412	5203	0	85576	703	14	918	44	5379	85776	715	121	5325	5578	37	3	3	5110	1	16	1	1	29389	25	80058	503	475	111	80000	80100	29331	29387	29582	29231	29553
160204	29244	218	2	1	0	0	0	0	6806	804	1	720	92	144	29291	784	391	1817	1893	2163	25	160158	80162	80000	80100	80000	400806	1291687	0	62	49	26264	29200	29253	9288	3	9218	160100	80200	80000	80200	80000	29298	35	1	1	80201	100	99	28	100	80000	100	80000	100	80912	54	349	6112	0	84958	672	9	868	34	4944	85454	602	141	5378	5269	55	3	4	5110	1	16	1	1	29410	21	80058	486	474	96	80000	80100	29260	29544	29391	29209	29358
160204	29110	219	3	0	0	0	0	0	7032	776	1	696	99	116	29151	775	378	1809	1873	2179	25	161367	80150	80000	80100	80000	400737	1295674	0	58	49	26289	29394	29254	9117	3	9182	160100	80200	80000	80200	80000	29335	35	1	1	80201	100	99	33	100	80000	100	80000	100	80946	51	423	5533	0	85483	678	12	933	70	5433	86125	728	124	4874	4508	52	4	4	5110	1	16	1	1	29412	28	80067	595	542	103	80000	80100	29168	29837	29385	29625	29610
160205	29450	218	3	2	0	3	0	0	6758	802	1	720	117	104	29303	781	349	1752	1834	2197	25	160159	80149	80000	80100	80000	400717	1307527	0	59	49	26034	29109	29407	9336	3	9388	160100	80200	80000	80200	80000	29260	35	1	1	80201	100	99	19	100	80000	100	80000	100	80947	52	433	6047	0	85486	707	16	868	40	5052	85704	825	128	4912	4979	53	2	2	5110	1	16	1	1	29171	29	80070	480	554	111	80000	80100	29610	29525	29443	29439	29373

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3651

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29799	221	3	0	1	0	0	0	7261	0	788	1	720	80	68	29233	789	378	1949	2193	1930	25	160075	80079	80000	80010	80000	400275	1292893	54	49	26253	29849	29582	9420	3	9054	160010	80020	80000	80020	80000	29153	35	1	1	80021	10	9	13	10	80000	10	80000	0	10	80936	63	445	5371	84978	756	13	915	130	5100	86157	847	138	4673	5130	33	0	3	5020	4	16	4	4	29308	34	80066	391	388	80	80000	80010	29308	29252	29301	29112	29292
160024	29199	219	3	0	3	0	0	0	6824	0	831	1	704	108	112	29164	789	370	1833	2213	1787	25	160064	80072	80000	80010	80000	400283	1295531	64	49	26355	29630	29473	9237	3	9353	160010	80020	80000	80020	80000	29178	35	1	1	80021	10	9	7	10	80000	10	80000	0	10	80967	52	423	5426	85925	821	11	937	34	4921	86007	800	140	5211	4746	49	0	0	5020	5	16	5	6	29001	19	80048	375	411	105	80000	80010	29133	29193	29165	29457	29352
160024	28928	217	4	0	0	0	0	0	6284	0	785	1	736	97	112	29226	802	347	2122	1907	1742	25	160068	80072	80000	80010	80000	400298	1290271	55	49	26089	29666	29314	9196	3	9351	160010	80020	80000	80020	80000	29296	35	1	1	80021	10	9	12	10	80000	10	80000	0	10	80945	71	425	5730	85135	703	13	875	132	5232	86187	747	124	4753	4314	68	0	3	5020	4	16	6	6	29058	24	80067	411	369	89	80000	80010	29345	29241	29285	29219	29449
160024	29108	220	3	0	3	3	0	0	7075	0	787	1	688	90	108	29127	794	302	2095	2419	1840	25	160070	80064	80000	80010	80000	400294	1284774	53	49	26293	29969	29322	9042	3	9177	160010	80020	80000	80020	80000	29087	35	1	1	80021	10	9	7	10	80000	10	80000	0	10	80896	32	408	5550	84718	702	16	861	90	4580	85701	721	124	5164	4706	35	0	3	5020	4	16	4	6	29340	26	80051	393	350	74	80000	80010	29248	29098	29112	29281	29062
160024	29153	218	3	0	0	3	0	0	7004	0	820	1	696	82	72	29122	741	363	1940	2209	1685	25	160063	80071	80000	80010	80000	400279	1293184	52	49	26010	29408	29209	9164	3	9240	160010	80020	80000	80020	80000	29231	35	1	1	80021	10	9	14	10	80000	10	80000	0	10	80933	35	421	5887	85338	705	11	869	24	4511	85958	786	125	5214	5177	32	0	5	5020	7	16	4	7	29239	24	80074	355	370	93	80000	80010	29267	29143	29140	29299	29202
160024	29298	219	2	0	0	2	0	0	6595	0	810	1	736	91	100	29022	777	311	2177	2274	1750	25	160078	80077	80000	80010	80000	400300	1292770	52	49	26237	29381	29370	9094	3	9199	160010	80020	80000	80020	80000	29193	35	1	1	80021	10	9	8	10	80000	10	80000	0	10	80922	33	406	5254	84624	652	13	888	38	4791	85572	868	130	5199	4841	70	0	3	5020	9	16	7	8	29079	30	80070	350	417	83	80000	80010	29259	29059	29480	29218	29137
160024	29309	218	3	0	0	0	0	0	7205	0	792	1	560	100	260	29197	798	372	2029	2081	1939	25	160067	80074	80130	80010	80000	400287	1289586	64	49	26033	29464	29272	9261	3	9023	160010	80020	80000	80020	80000	29389	35	1	1	80021	10	9	15	10	80000	10	80000	0	10	80940	34	461	5365	85116	700	13	895	38	4456	85664	709	121	5035	4708	14	0	2	5020	4	16	7	5	28987	26	80063	389	425	86	80000	80010	28954	29208	29179	29125	29051
160024	29264	220	1	0	0	0	0	0	7128	0	805	1	744	108	100	29309	806	347	2188	2184	1695	25	160056	80067	80000	80010	80000	400328	1285171	57	49	26076	29343	29302	9088	3	9057	160010	80020	80000	80020	80000	29194	35	1	1	80021	10	9	8	10	80000	10	80000	0	10	80953	34	389	5389	85515	700	16	917	76	5714	86023	706	126	5189	5121	37	0	3	5020	4	16	4	5	29130	21	80058	435	404	99	80000	80010	29322	29213	29185	29099	29175
160024	29091	219	1	0	0	0	0	1	7226	0	820	1	704	93	92	29279	771	365	2048	2136	2011	25	160076	80084	80000	80010	80000	400345	1293017	61	49	25975	29308	29148	9063	3	9259	160010	80020	80000	80020	80000	29051	35	1	1	80021	10	9	4	10	80000	10	80000	0	10	80919	16	417	5485	85771	745	10	930	32	5000	85860	726	113	5253	4506	18	0	0	5020	3	16	5	4	29029	21	80047	386	319	106	80000	80010	29138	29023	29006	29013	29109
160024	29141	218	2	1	1	0	0	0	6439	0	849	1	688	84	76	29286	801	302	1903	2147	1647	25	160061	80079	80000	80010	80000	400338	1283386	61	49	26021	29584	29344	9340	3	9205	160010	80020	80000	80020	80000	29266	35	1	1	80021	10	9	9	10	80000	10	80000	0	10	80886	17	421	5169	84790	706	13	891	32	5436	85836	723	124	5297	5226	17	0	3	5020	4	16	6	5	29278	24	80051	377	278	90	80000	80010	28979	29055	28984	29207	29119

LDRSB (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations