Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (shifted immediate, 32-bit)

Test 1: uops

Code:

  adds w0, w0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035800619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035700619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000100010354011100110001373127119931000100010361036103610361036
10041035700619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035700619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
10041035800619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
100410358012619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036

Test 2: Latency 1->2

Code:

  adds w0, w0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03181f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001001071022722999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036
10204100357500505992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000371022722999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035750061992068101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000371022722999510000101001003610036100361003610036
1020410035760061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035760061992025101001010010100647152149695510035100358656387321010010200102001003540111020110099100101001000071022722999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03191e3f4d5051schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064042722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
100241003575006199180481005810010100106472461496955100351003586783875410010100201002010035401110021109101001010003064022722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010010064022722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
100241003575006199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
100241003575106199180251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010203064022722999710000100101003610036100361003610036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  adds w0, w1, #3, lsl #12
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500611993025201002010020112129723314916955020035200351742571748620112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233049169550200352003517425717485201122022420224200356411202011009910020100101000481111320162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955020035200351742571748620112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955020035200351742571748620112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
20204200351490611993025201002010020112129723314916955020035200351742581748520112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955020035200351742571748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
202042003515002511993025201002010020112129723314916955020035200351742571748620112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955020035200351742581748620112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955020035200351742581748520112202242022420035641120201100991002010010100161111319162001220000201002003620036200362003620036
202042003515001681993025201002010020112129723314916955020035200351742571748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351500000000092619918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000000001270327211999520000200102003620036200362003620036
20024200351500000000012619918472001020010200101297247049169552003520035174283175042001020020200202003564112002110910200101001000000001270227111999520000200102003620036200362003620036
20024200351500000000016419918252001020010200101297247049169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036
2002420035150000000006119918252001020010200101297247049169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036
200242003515000000000251199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000110001270227221999520000200102003620036200362003620036
2002420035150000000006119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036
2002420035150000000006119918252001020010200101297247049169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036
2002420035150000000006119918252001020010200101297247049169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036
2002420035150000000006119918252001020010200101297247049169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036
20024200351500000000053619918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000000001270227221999520000200102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  adds w0, w8, #3, lsl #12
  adds w1, w8, #3, lsl #12
  adds w2, w8, #3, lsl #12
  adds w3, w8, #3, lsl #12
  adds w4, w8, #3, lsl #12
  adds w5, w8, #3, lsl #12
  adds w6, w8, #3, lsl #12
  adds w7, w8, #3, lsl #12
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267632010006963525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
8020426735200000079125801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
8020426735200000079325801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000015110119112673180000801002673626736267362673626736
8020426735200000083825801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
8020426735200000071725801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
8020426735200000090525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
802042673520000007612580100801008010040050004923655267352673516672316690801008020080200267353911802011009910080100100000526005110119112673180000801002673626736267362673626736
8020426735200000087825801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
8020426735200000088225801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000005110119112673180000801002673626736267362673626736
80204267352000000352580100801008010040050004923655267352673516672316690801008020080200267353911802011009910080100100000174005110119112673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426722200000000056258001080010800104000500492362526705267051666531668380010800208002026705391180021109108001010000000050200818532670280000800102670626706267062670626706
8002426705200000000077258001080010800104000500492362526705267051666531668380010800208002026705391180021109108001010000000050200318552670280000800102670626706267062670626706
8002426705200000000035258001080010800104000500492362526705267051666531668380010800208002026705391180021109108001010000000050200318452670280000800102670626706267062670626706
8002426705200000000035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010000003050200318552670280000800102670626706267062670626706
80024267052000003012035258001080010800104000500492362526705267051666531668380010800208002026705391180021109108001010000000050200318462670280000800102670626706267062670626706
8002426705200000000035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010000000050200518352670280000800102670626706267062670626706
80024267051990000000352580010800108001040005014923625267052670516665161668380010800208002026705391180021109108001010000000050200518552670280000800102670626706267062670626706
8002426705200000000035258001080010800104000500492362526705267051666531668380010800208002026705391180021109108001010000000050200518642670280000800102670626706267062670626706
8002426705200000000035258001080010800104000500492362526705267051666531668380010800208002026705391180021109108001010000000050200318462670280000800102670626706267062670626706
80024267962000000000351098001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010000000050200418652670280000800102670626706267062670626706