Firestorm: LDR (register, 32-bit) measurements

Code:

  ldr w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	402	2	1	1	45	1	0	1	383	2	12	1	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	391	14	10	7	1000	395	399	395	399	399
1004	395	3	1	1	45	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	1	1	45	0	0	1	383	2	1	12	19	25	1000	1000	1000	15037	1	394	398	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	45	1	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	398	398	217	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	395	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	45	1	0	1	382	2	12	1	19	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	395	395
1004	398	2	0	0	44	1	0	1	382	2	1	1	19	25	1000	1000	1000	15274	0	398	398	217	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	2	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	44	1038	0	39	1039	6	1	38	44	73	1	16	1	1	391	14	14	7	1000	399	399	399	399	399
1004	394	3	0	0	47	1	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	44	1038	3	38	1038	6	1	38	44	73	1	16	1	1	391	10	10	4	1000	399	395	395	395	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	1	398	398	216	3	259	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	44	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	524	0	0	1	0	0	0	0	70020	69764	59709	25	40104	30103	10001	30100	10000	616175	3342206	0	49	66970	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	1	2610	1	71	1	1	69813	30003	6	0	9	10000	30100	70051	70036	70036	70048	70051
40204	70050	524	0	0	1	1	0	1	0	70032	69764	59709	25	40100	30103	10001	30100	10000	616175	3341470	0	49	66970	0	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	0	1	2610	1	71	1	1	69813	30003	6	0	9	10000	30100	70051	70036	70051	70048	70036
40204	70050	524	0	0	0	0	0	1	0	70020	69764	59695	25	40104	30103	10000	30100	10000	616015	3341470	0	49	66967	0	70050	70035	64646	3	64938	40100	30200	10000	60200	20000	70050	81	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2610	1	71	1	1	69813	30003	6	6	9	10000	30100	70051	70048	70051	70051	70036
40204	70047	525	0	0	0	0	0	1	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66970	0	70050	70035	64631	3	64938	40100	30847	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10003	0	1	2610	1	71	1	1	69798	30000	0	6	9	10000	30100	70051	70051	70051	70051	70036
40204	70035	524	0	0	0	0	0	0	0	70020	69781	59695	25	40104	30103	10001	30100	10000	616005	3341470	0	49	66970	0	70050	70050	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	2610	1	71	1	1	69810	30003	0	0	0	10000	30100	70051	70051	70051	70051	70036
40204	70050	525	0	0	0	0	1	0	0	70020	69735	59706	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66971	0	70035	70051	64631	3	64941	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	0	10000	1	1	2610	1	17	1	1	69798	30003	9	0	9	10000	30100	70036	70051	70051	70048	70051
40204	70050	525	0	0	0	0	0	0	0	70020	69781	59706	25	40104	30103	10000	30100	10000	616005	3341470	0	49	66955	0	70047	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	0	2610	1	71	1	1	69798	30000	0	6	0	10000	30100	70036	70051	70051	70051	70051
40204	70050	525	0	0	0	0	1	0	0	70061	69781	59709	25	40100	30100	10001	30100	10000	616005	3342062	0	49	66970	0	70050	70050	64643	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	3	10000	1	1	2610	1	71	1	1	69798	30003	9	9	9	10000	30100	70048	70048	70048	70036	70050
40204	70047	524	0	0	0	0	6	0	0	70020	69764	59709	25	40104	30100	10000	30100	10000	616050	3342206	0	49	66970	0	70050	70098	64643	3	64956	40100	30365	10054	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10003	1	1	2610	1	71	1	1	69798	30003	9	9	9	10000	30100	70051	70036	70051	70051	70036
40204	70047	525	0	0	0	0	1	1	0	70035	69764	59695	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66970	0	70050	70050	64646	3	65034	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	0	2610	1	71	1	1	69798	30000	6	6	0	10000	30100	70048	70036	70051	70036	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	0	0	1	1	0	70032	69728	59695	25	40014	30010	10002	30010	10000	616952	3341470	1	0	49	66967	70050	70035	64665	3	64972	40010	30020	10000	60020	20000	70160	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	0	2520	0	0	0	1	71	3	2	69813	30003	9	6	6	10000	30010	70048	70048	70051	70048	70048
40024	70047	524	0	0	0	0	1	0	0	70035	69728	59695	25	40014	30013	10001	30010	10000	616982	3341470	1	0	49	66970	70050	70050	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	2520	0	0	0	1	71	2	1	69813	30003	6	0	6	10000	30010	70048	70036	70048	70051	70036
40024	70047	524	0	0	0	0	109	1	0	70032	69748	59709	25	40014	30013	10001	30010	10000	616961	3342062	1	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	0	0	0	0	2520	0	0	0	2	71	2	1	69798	30003	6	6	6	10000	30010	70048	70036	70036	70048	70048
40024	70047	525	0	0	0	0	1	0	0	70020	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	0	49	66967	70035	70035	64665	3	64972	40010	30020	10000	60020	20000	70151	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	2520	0	0	0	1	71	3	2	69810	30003	6	0	6	10000	30010	70048	70048	70036	70048	70048
40024	70035	525	0	0	0	0	1	0	0	70032	69760	59709	25	40014	30013	10001	30010	10000	616982	3342062	1	0	49	66955	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	2520	0	0	0	1	71	1	2	69810	30003	6	0	0	10000	30010	70054	70049	70048	70048	70048
40024	70035	525	0	0	0	0	1	0	0	70032	69728	59706	42	40014	30013	10000	30010	10000	616952	3342062	1	0	49	66967	70047	70047	64654	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	0	2520	0	0	0	1	71	2	1	69810	30003	6	6	0	10000	30010	70048	70048	70048	70048	70048
40024	70050	524	0	0	0	0	6	0	0	70032	69729	59706	25	40014	30013	10000	30010	10000	616982	3341470	1	0	49	66967	70047	70047	64665	3	64960	40010	30020	10000	60020	20000	70113	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	0	1	0	2520	0	0	0	1	71	1	2	69813	30003	6	6	6	10000	30010	70051	70048	70048	70051	70048
40024	70035	524	0	0	0	0	1	0	0	70020	69728	59706	25	40014	30010	10001	30010	10000	616952	3342062	1	0	49	66970	70047	70047	64668	3	64985	40010	30020	10000	60020	20000	70120	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	24	10000	1	0	0	0	2520	0	0	0	2	71	1	2	69810	30003	0	6	9	10000	30010	70048	70051	70036	70048	70036
40024	70035	524	0	0	0	0	1	0	0	70032	69728	59706	25	40014	30010	10001	30010	10000	617068	3342206	1	0	49	66955	70047	70047	64668	3	64960	40010	30020	10000	60020	20000	70151	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	1	0	2520	0	0	0	2	71	1	1	69813	30003	0	6	6	10000	30010	70048	70036	70051	70048	70099
40024	70035	525	0	0	0	0	1	1	0	70032	69728	59706	25	40014	30010	10000	30010	10000	617176	3342062	1	0	49	66970	70090	70035	64668	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	36	10000	0	0	0	0	2520	0	0	0	2	71	2	3	69813	30003	6	6	0	10000	30010	70048	70048	70048	70036	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	0	0	1	0	0	1	2	1	0	70020	69782	59713	25	40104	30103	10002	30100	10000	616041	3342254	1	49	66974	70035	70035	64650	3	64950	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	2	0	10002	52	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69798	30000	0	10	0	10000	30100	70052	70055	70036	70036	70036
40204	70051	524	0	0	0	0	0	0	0	1	0	70036	69764	59695	25	40104	30100	10001	30100	10000	616041	3342398	1	49	66955	70054	70054	64631	3	65049	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30003	0	10	0	10000	30100	70052	70052	70052	70036	70036
40204	70035	525	0	0	0	0	0	0	1	0	0	70039	69785	59713	25	40100	30103	10001	30100	10000	616175	3342254	0	49	66974	70054	70054	64631	3	65022	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69880	30003	0	10	13	10000	30100	70057	70055	70052	70036	70055
40204	70035	524	0	0	0	0	0	0	0	0	0	70039	69785	59695	25	40104	30103	10001	30100	10000	616175	3341470	1	49	66974	70054	70054	64631	3	65040	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69798	30003	10	13	10	10000	30100	70052	70052	70055	70052	70055
40204	70054	524	0	0	0	0	0	0	1	1	0	70039	69785	59710	25	40100	30100	10000	30100	10000	616041	3341470	0	49	66955	70035	70035	64650	3	65006	40894	30200	10000	60200	20000	70059	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2610	1	71	1	1	69798	30000	0	0	13	10000	30100	70055	70036	70055	70055	70055
40204	70054	524	0	0	0	0	0	0	1	1	0	70036	69782	59713	25	40100	30103	10001	30100	10000	616175	3342398	1	49	66955	70054	70035	64631	3	65039	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30003	13	0	13	10000	30100	70036	70055	70055	70052	70055
40204	70054	525	0	0	0	0	0	0	1	1	0	70043	69785	59713	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66971	70054	70054	64631	3	65050	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69817	30003	0	10	13	10000	30100	70055	70052	70055	70036	70055
40204	70035	525	0	0	0	0	0	0	4	1	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616175	3342398	1	49	66974	70035	70054	64631	3	65039	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30003	0	0	13	10000	30100	70036	70036	70036	70055	70055
40204	70051	525	0	0	0	0	0	0	1	1	0	70095	69785	59713	25	40104	30103	10000	30100	10000	616041	3342254	1	49	66974	70054	70035	64631	3	65068	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69798	30003	13	10	13	10000	30100	70052	70055	70052	70036	70036
40204	70051	525	0	0	0	0	1	1	1	0	0	70039	69785	59713	25	40100	30100	10000	30100	10000	616086	3342638	1	49	66974	70054	70054	64647	3	65038	40892	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69798	30000	0	13	13	10000	30100	70055	70055	70036	70055	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70206	524	1	1	1	0	1	0	1	176	0	0	0	1	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342206	0	49	66968	70035	70047	64668	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	1	71	2	1	69813	30003	9	6	9	10000	30010	70051	70036	70051	70041	70048
40024	70047	525	0	0	0	1	1	0	13	0	1	0	0	0	70034	69760	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66955	70047	70035	64653	3	64960	40010	30020	10220	60020	20436	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	1	0	0	2520	1	71	1	1	69813	30003	0	0	9	10000	30010	70051	70051	70051	70036	70036
40024	70050	525	0	0	0	1	0	0	1	0	1	0	0	0	70032	69728	59741	25	40014	30013	10001	30010	10000	617104	3342062	0	49	66967	70035	70050	64668	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	1	71	1	1	69810	30003	6	9	9	10000	30010	70048	70048	70048	70036	70048
40024	70047	525	0	0	0	0	0	0	1	0	0	0	0	0	70035	69743	59706	25	40014	30013	10001	30010	10000	616982	3342062	0	49	66967	70050	70035	64653	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	0	2520	1	71	1	1	69810	30000	9	9	9	10000	30010	70036	70051	70036	70048	70036
40024	70047	525	0	0	0	0	0	0	1	0	1	0	0	0	70032	69728	59695	25	40014	30013	10001	30010	10000	616952	3345602	0	49	66955	70050	70090	64665	3	64982	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	0	0	0	0	0	2520	1	71	1	1	69810	30003	9	6	9	10000	30010	70051	70036	70079	70048	70036
40024	70058	525	0	0	0	0	0	0	1	0	0	0	0	0	70020	69760	59695	25	40010	30010	10001	30010	10000	616982	3342206	0	49	66955	70047	70047	64668	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	1	71	1	1	69810	30003	0	9	6	10000	30010	70036	70051	70051	70048	70048
40024	70047	524	0	0	0	1	1	0	0	0	0	0	0	0	70020	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66967	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	1	0	10000	1	0	0	0	0	2520	1	71	1	1	69813	30003	9	6	9	10000	30010	70048	70048	70048	70051	70051
40024	70050	524	0	0	0	0	0	0	1	0	0	0	0	0	70032	69728	59706	25	40014	30010	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10003	1	0	10000	1	1	0	0	0	2520	2	71	1	1	69810	30000	9	0	0	10000	30010	70036	70051	70048	70048	70048
40024	70047	524	0	0	0	0	0	0	6	0	1	0	0	0	70032	69760	59706	25	40014	30013	10001	30010	10000	616982	3341470	0	49	66955	70035	70050	64668	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	2	71	2	1	69798	30003	6	6	0	10000	30010	70048	70048	70036	70048	70048
40024	70035	524	0	0	0	0	0	0	1	0	1	0	0	0	70020	69728	59706	25	40014	30013	10001	30010	10000	619245	3342062	0	49	66967	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70051	70036	70051	70048	70048

Test 4: throughput

Count: 8

Code:

  ldr w0, [x6, x7]
  ldr w0, [x6, x7]
  ldr w0, [x6, x7]
  ldr w0, [x6, x7]
  ldr w0, [x6, x7]
  ldr w0, [x6, x7]
  ldr w0, [x6, x7]
  ldr w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	1	1	0	0	77	1	0	3	26718	2	18	18	1	25	80100	100	80000	100	80016	500	1175101	0	49	23652	27307	26725	16659	6	16688	80116	200	80024	200	160048	26737	87	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80057	1	0	0	59	80038	6	1	57	42	19	3	1	1	1	5118	0	16	0	0	26711	0	9	9	2	80000	100	26733	26733	26733	26733	26715
80204	26732	200	1	1	1	0	0	65	0	0	3	26717	2	18	0	15	25	80100	100	80000	100	80014	500	1167493	1	49	23639	26736	26736	16660	6	16684	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	0	80019	1	0	1	59	80038	6	1	57	0	19	0	1	1	1	5118	0	16	0	0	26729	0	9	9	2	80000	100	26734	26734	26715	26733	26715
80204	26732	200	1	1	0	0	0	65	0	0	3	26718	2	18	18	0	25	80100	100	80000	100	80015	500	1167579	0	49	23657	26724	26737	16642	6	16666	80116	200	80024	200	160048	26714	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80057	1	0	0	21	80038	0	1	57	42	19	0	1	1	1	5118	0	16	0	0	26731	0	9	0	2	80000	100	26735	26715	26715	26715	26715
80204	26714	200	1	0	0	0	0	64	0	0	1	26699	0	18	18	18	25	80100	100	80000	100	80016	500	1166590	1	49	23654	26736	26734	16659	6	16684	80115	200	80024	200	160048	26714	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80057	1	0	2	22	80038	0	1	57	0	19	0	1	1	1	5118	0	16	0	0	26729	0	6	0	0	80000	100	26733	26715	26733	26733	26733
80204	26714	200	1	0	1	0	0	65	0	0	2	26699	0	18	0	15	25	80100	100	80000	100	80016	500	1167763	1	49	23655	26737	26750	16660	6	16666	80115	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	0	80057	1	0	1	59	80038	6	0	57	42	19	2	1	1	1	5118	0	16	0	0	26729	0	9	9	2	80000	100	26733	26733	26715	26733	26733
80204	26732	200	1	1	1	0	0	65	0	0	2	26718	2	18	0	0	25	80100	100	80000	100	80015	500	1167250	0	49	23655	26732	26732	16666	6	16684	80115	200	80024	200	160048	26714	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	21	40	80057	1	0	1	58	80000	6	0	57	42	19	0	1	1	1	5118	0	16	0	0	26729	0	9	9	2	80000	100	26716	26715	26734	26734	26733
80204	26732	200	1	1	1	1	0	110	0	0	3	26699	2	18	18	1	25	80100	100	80000	100	80015	500	1167763	0	49	23635	26748	26745	16660	6	16685	80115	200	80024	200	160048	26732	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80056	0	0	0	59	80000	6	1	56	42	19	0	1	1	1	5118	0	16	0	0	26747	0	0	9	2	80000	100	26733	26733	26733	26733	26733
80204	26732	200	1	1	0	0	0	65	1	0	2	26700	2	0	18	16	25	80100	100	80000	100	80022	500	1166730	1	49	23657	26734	26749	16650	10	16654	80122	200	80030	200	160060	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80019	0	0	0	59	80038	0	0	57	0	19	0	2	2	2	5129	1	23	1	1	26711	0	9	0	2	80000	100	26733	26733	26733	26733	26822
80204	26754	201	1	1	0	0	0	21	1	0	2	26700	0	18	0	16	25	80100	100	80000	100	80022	500	1167274	1	49	23654	26734	26724	16650	9	16654	80121	200	80030	200	160060	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80019	0	0	0	59	80038	6	1	57	0	19	1	2	2	2	5128	1	23	1	1	26711	0	9	0	0	80000	100	26715	26733	26733	26733	26733
80204	26715	200	1	1	0	0	1	65	0	0	3	26717	2	18	18	15	25	80100	100	80000	100	80021	500	1169278	0	49	23639	26735	26732	16632	10	16654	80120	200	80030	200	160060	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80019	1	0	0	59	80000	6	0	19	42	19	1	2	2	2	5129	1	23	1	1	26729	0	9	9	2	80000	100	26733	26715	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	201	1	0	1	1	0	79	0	0	3	26721	3	7	9	20	25	80010	10	80000	10	80000	50	1167791	0	49	23657	26912	26802	16665	3	16717	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	80058	1	0	1	61	80040	6	1	59	43	19	0	0	5020	16	16	6	17	26733	13	13	5	80000	10	26738	26738	26716	26738	26737
80024	26736	200	1	1	0	0	0	85	0	1	3	26721	3	7	7	19	25	80010	10	80000	10	80000	50	1173975	0	49	23656	26879	26840	16713	3	16716	80010	20	80000	20	160000	26715	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	80059	1	0	1	61	80039	6	0	59	43	19	0	0	5020	17	16	8	17	26733	0	13	5	80000	10	26737	26716	26716	26737	26737
80024	26736	201	1	0	1	0	0	93	0	1	2	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1167219	1	49	23635	26715	26798	16668	3	16694	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	80059	1	0	0	61	80039	6	1	58	43	19	0	0	5020	14	16	7	17	26734	13	13	5	80000	10	26715	26737	26737	26737	26737
80024	26736	200	1	0	1	0	0	91	0	1	3	26722	2	7	7	1	25	80010	10	80000	10	80000	50	1168283	0	49	23634	26737	26783	16665	3	16716	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	45	80059	0	0	1	61	80000	6	1	59	43	19	0	0	5020	8	16	8	17	26733	13	0	5	80000	10	26738	26737	26716	26738	26737
80024	26736	200	1	1	0	0	0	21	0	1	1	26700	2	7	0	0	25	80010	10	80000	10	80000	50	1167298	1	49	23656	26736	26831	16686	3	16694	80010	20	80000	20	160000	26736	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	80058	1	0	1	63	80039	6	0	58	0	19	0	0	5020	8	16	6	17	26733	13	13	0	80000	10	26737	26738	26737	26716	26737
80024	26714	200	1	0	0	0	0	79	0	1	2	26721	3	7	0	19	25	80010	10	80000	10	80000	50	1173975	0	49	23656	26736	26715	16681	3	16800	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	80059	0	0	0	61	80039	6	1	19	0	19	0	0	5020	6	16	17	8	26733	13	13	5	80000	10	26737	26737	26716	26738	26737
80024	26736	200	1	0	1	0	0	67	0	1	2	26721	3	0	0	19	25	80010	10	80000	10	80000	50	1173975	0	49	23656	26737	26797	16689	3	16717	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	80060	1	0	1	61	80041	6	1	58	43	19	0	0	5020	14	16	17	17	26734	13	13	5	80000	10	26737	26737	26737	26737	26716
80024	26737	201	1	0	0	0	0	345	0	0	0	26699	3	7	7	0	25	80010	10	80000	10	80000	50	1173975	0	49	23656	26737	26777	16692	3	16695	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	0	80059	0	0	1	61	80000	6	1	58	43	19	0	0	5020	17	16	17	8	26734	13	13	5	80000	10	26737	26739	26737	26737	26716
80024	26736	200	1	1	1	0	0	94	0	1	3	26721	3	7	7	1	25	80010	10	80000	10	80000	50	1168286	0	49	23635	26736	26832	16689	3	16716	80010	20	80000	20	160000	26736	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	0	80019	0	0	1	61	80000	6	1	58	0	19	0	0	5020	17	16	17	8	26734	13	13	5	80000	10	26716	26737	26739	26737	26742
80024	26737	200	1	1	1	1	0	291	0	0	3	26721	3	7	0	19	25	80010	10	80000	10	80000	50	1174119	0	49	23656	26737	26736	16682	3	16850	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	43	80059	1	0	0	61	80039	6	0	19	43	19	0	0	5020	17	16	17	17	26733	13	0	5	80000	10	26715	26737	26737	26737	26870

LDR (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations