Firestorm: LDR (register, uxtw, 32-bit) measurements

Code:

  ldr w0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	0	1	1	0	66	1	0	3	388	2	7	7	19	25	1000	1000	1000	15555	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	21	43	1059	0	0	60	1039	6	1	58	43	19	2	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	403	3	1	1	1	1	0	0	67	0	0	2	388	3	7	7	19	25	1000	1000	1000	15555	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1059	0	0	60	1040	6	1	59	43	19	1	73	1	16	1	1	403	13	13	5	1000	404	404	404	404	403
1004	403	3	1	0	1	0	1	1	67	1	0	2	388	3	7	7	20	25	1000	1000	1000	15555	403	403	225	3	261	1000	1000	2000	404	85	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	60	1039	6	1	59	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	403	2	1	1	1	0	0	0	93	0	0	3	388	3	7	7	19	25	1000	1000	1000	15525	403	403	225	3	260	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1021	20	43	1059	1	0	60	1040	6	1	60	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	403	404	404	404
1004	403	3	1	1	0	1	0	0	67	0	0	3	388	3	7	7	19	25	1000	1000	1000	15480	403	403	225	3	260	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	20	43	1058	1	0	60	1040	6	1	58	43	19	2	73	1	16	1	1	399	13	13	5	1000	404	404	404	404	404
1004	403	3	1	0	0	1	0	0	66	0	0	2	388	2	7	7	20	25	1000	1000	1000	15506	403	403	226	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1059	0	0	61	1040	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	403	404	404	404	404
1004	403	3	1	1	1	1	0	0	66	0	0	2	388	2	7	7	20	25	1000	1000	1000	15506	402	403	225	3	260	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	19	43	1059	1	0	61	1039	6	1	59	43	19	1	73	1	16	1	1	399	13	13	5	1000	403	404	404	404	404
1004	403	3	1	0	1	1	0	0	66	0	0	2	387	2	7	7	19	25	1000	1000	1000	15480	405	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1058	0	0	60	1040	6	1	60	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	408	3	1	0	0	0	0	0	76	0	0	2	388	3	7	7	19	25	1000	1000	1000	15524	411	403	228	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	61	1040	6	1	58	43	19	2	73	1	16	1	1	400	13	13	5	1000	404	403	404	404	404
1004	403	4	1	0	1	0	0	0	66	0	0	2	388	2	7	7	18	25	1000	1000	1000	15524	402	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	60	1040	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	0	0	1	0	1	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616175	3342254	1	49	66971	70092	70051	64631	3	64952	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	10	0	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	0	0	1	1	1	70042	69788	59701	25	40104	30106	10002	30100	10000	616068	3341769	1	49	66977	70060	70041	64653	3	64944	40100	30200	10000	60200	20000	70062	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30006	10	10	10	10000	30100	70058	70058	70058	70058	70042
40204	70057	525	1	0	0	1	0	0	0	2	1	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69798	30000	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	0	0	1	1	70042	69788	59716	25	40108	30103	10001	30100	10000	616068	3342542	1	49	66977	70057	70057	64637	3	64960	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30006	10	10	10	10000	30100	70042	70058	70058	70058	70058
40204	70057	525	1	1	1	0	0	0	0	2	0	0	70036	69782	59710	25	40104	30112	10000	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	3	64946	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10001	0	2	1	10000	0	1	0	1	2	0	2610	1	71	1	1	69820	30003	10	0	13	10000	30100	70052	70036	70052	70052	70036
40204	70051	525	0	0	0	0	0	0	0	1	1	0	70020	69782	59710	25	40100	30103	10000	30100	10000	616014	3342254	1	49	66971	70035	70035	64631	3	64954	40100	30200	10000	60200	20000	70052	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10002	0	0	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69804	30000	0	0	10	10000	30100	70036	70052	70052	70052	70036
40204	70035	525	0	0	0	0	1	0	0	0	0	1	70026	69702	59716	25	40108	30106	10002	30100	10000	616078	3342542	0	49	63931	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10001	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	2	69798	30006	10	0	10	10000	30100	70052	70036	70036	70036	70036
40204	70035	524	0	0	0	0	0	0	0	1	0	1	70042	69788	59701	25	40108	30106	10002	30100	10000	616078	3342542	0	49	66977	70057	70041	64653	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70055	70052	70036	70052	70036
40204	70061	526	0	0	0	0	0	0	0	1	1	0	70020	69782	59695	25	40104	30100	10001	30100	10000	616175	3341470	0	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	0	1	10000	0	1	1	1	0	0	2610	1	71	1	1	69820	30003	10	10	10	10000	30100	70036	70052	70052	70036	70036
40204	70051	524	0	0	0	0	1	1	0	1	0	0	70040	69782	59710	25	40100	30103	10001	30100	10000	616175	3341470	0	49	66971	70035	70035	64631	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	0	10	10000	30100	70058	70042	70042	70058	70058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	1	0	0	1	0	0	2	0	1	0	1	70044	69780	59715	25	40018	30016	10002	30010	10000	619212	3342350	0	49	66976	70041	70056	64674	0	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	1	0	10002	0	0	1	10000	1	1	0	1	0	0	0	2520	1	71	1	1	69902	30006	9	6	0	10000	30010	70042	70054	70057	70057	70057
40024	70056	524	1	0	1	1	0	0	2	0	0	0	0	70041	69780	59715	25	40014	30016	10002	30010	10000	617036	3341769	0	49	66973	70041	70041	64674	0	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10002	0	0	1	10000	1	1	0	1	0	0	0	2520	1	71	1	1	69884	30006	6	6	9	10000	30010	70057	70057	70057	70057	70057
40024	70056	524	1	1	0	0	0	0	2	0	0	0	0	70041	69780	59701	25	40014	30013	10002	30010	10000	617036	3342494	0	49	66961	70041	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70056	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	1	10000	1	1	1	1	1	0	0	2520	1	71	2	1	69897	30003	9	9	9	10000	30010	70042	70042	70054	70042	70054
40024	70041	524	1	0	1	0	0	0	1	0	0	0	1	70041	69780	59717	25	40018	30013	10002	30010	10057	616995	3342494	0	49	66976	70056	70041	64659	0	3	64981	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10001	0	1	1	10000	0	1	0	1	0	0	0	2520	1	71	1	2	69904	30006	0	0	0	10000	30010	70042	70057	70042	70054	70054
40024	70056	524	1	1	0	1	0	0	1	0	0	0	0	70038	69777	59712	25	40018	30016	10002	30010	10000	616995	3342494	0	49	66961	70053	70056	64671	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	0	0	2520	1	71	1	1	69893	30006	0	6	0	10000	30010	70057	70042	70042	70057	70057
40024	70056	525	1	0	0	0	0	0	7	0	0	0	0	70026	69702	59715	25	40014	30016	10002	30010	10000	617009	3342494	0	49	66976	70053	70041	64674	0	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	1	2	1	10000	1	1	0	1	0	0	0	2520	1	71	1	1	69884	30006	6	6	9	10000	30010	70057	70042	70042	70057	70054
40024	70056	524	1	1	1	1	0	0	1	0	0	0	0	70026	69702	59712	25	40014	30016	10002	30010	10000	616995	3342350	0	49	66961	70056	70056	64659	0	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10001	0	0	1	10000	0	1	0	1	1	0	0	2520	1	71	1	1	69895	30006	0	6	0	10000	30010	70063	70049	70054	70054	70057
40024	70053	525	1	1	1	0	0	0	2	0	0	0	0	70041	69777	59701	25	40018	30016	10002	30010	10000	617009	3342494	0	49	66973	70041	70053	64671	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	1	10000	0	1	0	1	2	0	0	2520	1	71	1	1	69893	30006	9	6	6	10000	30010	70057	70054	70054	70042	70057
40024	70053	525	1	1	0	0	0	1	2	0	0	0	0	70038	69780	59712	25	40014	30013	10002	30010	10000	617036	3341769	0	49	66976	70056	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	1	0	1	10000	1	1	1	1	1	0	0	2520	1	71	1	1	69848	30006	9	6	0	10000	30010	70054	70057	70057	70057	70057
40024	70056	524	1	1	1	1	0	0	1	0	0	0	1	70038	69702	59715	25	40014	30016	10002	30010	10000	617036	3341769	0	49	66976	70053	70053	64674	0	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	0	1	10000	1	1	0	1	0	0	0	2520	1	71	1	1	69910	30006	9	6	9	10000	30010	70054	70054	70057	70057	70057

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	1	1	1	1	1	70020	69781	59706	25	40104	30100	10002	30251	10000	616175	3342206	1	49	66967	70050	70050	64643	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10004	0	10000	7	0	10000	1	0	0	0	0	2610	1	71	1	1	69798	30003	9	0	6	10000	30100	70048	70036	70048	70036	70051
40204	70047	525	0	0	0	0	1	70020	69781	59709	25	40100	30103	10001	30100	10000	616005	3342206	1	49	66970	70035	70035	64646	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69798	30000	9	9	0	10000	30100	70051	70036	70051	70051	70051
40204	70047	524	0	0	0	4	1	70035	69764	59709	25	40104	30103	10013	30269	10000	616005	3342206	0	49	66967	70035	70050	64643	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69813	30003	0	9	6	10000	30100	70051	70051	70036	70048	70051
40204	70050	525	0	0	0	1	1	70032	69764	59709	25	40100	30103	10001	30100	10000	616015	3341470	1	49	66970	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	3	10000	1	1	0	0	0	2610	1	71	1	1	69798	30003	6	0	0	10000	30100	70051	70051	70036	70036	70051
40204	70035	525	0	0	0	1	1	70035	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	70035	70047	64646	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69813	30003	0	0	9	10000	30100	70051	70036	70048	70048	70051
40204	70050	524	0	1	0	1	1	70020	69764	59709	25	40100	30103	10000	30100	10000	616175	3342062	0	49	66970	70050	70035	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	0	10000	0	0	0	0	0	2610	1	71	1	1	69813	30003	0	6	0	10000	30100	70051	70054	70048	70051	70051
40204	70050	525	0	0	0	1	1	70020	69764	59706	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69798	30003	0	6	0	10000	30100	70051	70051	70036	70051	70051
40204	70050	525	0	0	0	1	1	70020	69781	59709	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66970	70050	70047	64631	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69798	30000	9	9	9	10000	30100	70036	70051	70036	70051	70036
40204	70035	524	0	1	1	1	1	70020	69781	59709	25	40104	30103	10001	30100	10000	616015	3342206	1	49	63943	70050	70035	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69813	30006	9	0	0	10000	30100	70051	70051	70036	70051	70051
40205	70035	524	0	0	1	1	1	70035	69764	59695	25	40104	30103	10000	30100	10000	616175	3341470	0	49	66970	70050	70047	64631	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	3	10000	1	1	0	0	0	2610	1	71	1	1	69798	30000	9	6	6	10000	30100	70036	70048	70051	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	18	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	524	0	1	0	0	0	1	1	0	70020	69743	59713	25	40014	30013	10001	30010	10000	616991	3342398	0	49	67066	70035	70035	64653	0	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	2520	11	71	7	7	69814	30000	13	0	13	10000	30010	70292	70163	70036	70036	70036
40024	70054	525	0	0	0	0	0	0	0	0	70039	69778	59713	25	40014	30013	10001	30010	10000	617068	3342254	0	49	66981	70051	70054	64672	0	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	2520	9	71	9	9	69817	30003	0	13	10	10000	30010	70036	70055	70055	70055	70036
40024	70054	525	0	0	0	0	0	0	0	0	70039	69743	59713	25	40014	30013	10001	30010	10000	617068	3342254	0	49	66955	70054	70051	64672	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	2520	8	71	6	6	69814	30003	0	13	10	10000	30010	70036	70052	70052	70052	70055
40024	70051	525	0	0	1	0	0	1	1	0	70020	69778	59695	25	40014	30013	10001	30010	10000	617018	3341470	0	49	66974	70035	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	2520	6	71	6	8	69817	30000	13	0	13	10000	30010	70052	70055	70055	70052	70055
40024	70051	524	0	0	0	0	0	1	0	0	70020	69776	59710	25	40014	30013	10001	30010	10000	617090	3341470	0	49	66974	70035	70035	64672	0	3	64976	40010	30020	10000	60020	20000	70035	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	0	2520	8	71	7	9	69798	30003	13	13	13	10000	30010	70055	70036	70055	70036	70060
40024	70054	525	0	0	0	0	0	1	0	0	70039	69778	59713	25	40010	30013	10000	30010	10000	617018	3342398	0	49	66974	70054	70035	64653	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	2620	7	71	8	8	70230	30000	13	13	13	10000	30010	70036	70380	70052	70052	70400
40024	70051	525	0	0	0	0	0	1	0	0	70036	69743	59710	25	40014	30010	10001	30010	10000	617018	3342398	0	49	66971	70035	70054	64653	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	2520	6	71	6	9	69814	30003	13	13	0	10000	30010	70036	70055	70077	70052	70055
40024	70039	525	0	0	0	0	0	0	0	0	70020	69743	59710	25	40014	30013	10000	30010	10000	617068	3342254	0	49	66974	70054	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	2520	9	71	6	8	69814	30003	13	13	10	10000	30010	70052	70052	70055	70036	70055
40024	70054	525	0	0	0	0	0	0	0	0	70020	69778	59713	25	40010	30013	10000	30010	10000	616991	3341470	0	49	66971	70054	70054	64669	0	3	64960	40010	30020	10000	60020	20134	70055	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	2520	6	71	6	8	69817	30003	13	10	13	10000	30010	70055	70060	70052	70055	70052
40024	70054	525	0	0	0	0	0	6	1	0	70039	69778	59713	25	40014	30010	10001	30010	10000	617018	3342398	0	49	66971	70054	70035	64672	0	3	64960	40218	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	2520	8	71	10	6	69817	30000	13	0	13	10000	30010	70052	70052	70055	70052	70055

Test 4: throughput

Count: 8

Code:

  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]
  ldr w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	1	1	67	0	0	0	1	26716	2	0	1	0	25	80100	100	80000	100	80013	500	1166836	1	49	23639	26731	26731	16655	6	16688	80115	200	80024	200	160048	26736	64	1	1	80201	100	99	0	100	80000	100	80000	100	80021	20	43	80058	1	0	0	21	80000	6	1	39	44	0	0	1	1	1	5118	0	16	0	0	26734	0	0	13	0	80000	100	26738	26738	26738	26737	26715
80204	26736	200	1	1	1	0	0	0	1	0	0	0	26716	2	1	0	21	25	80100	100	80000	100	80015	500	1168380	1	49	23656	26736	26714	16663	6	16689	80116	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	100	80019	19	43	80059	1	0	1	60	80040	0	1	39	43	0	0	1	1	1	5118	0	16	0	0	26724	0	14	14	4	80000	100	26732	26708	26732	26732	26732
80204	26731	201	0	0	0	0	0	67	1	0	0	0	26721	0	7	7	19	25	80100	100	80000	100	80015	500	1169949	1	49	23627	26731	26707	16659	6	16679	80115	200	80024	200	160048	26731	77	1	1	80201	100	99	0	100	80000	100	80000	100	80021	20	43	80061	0	0	0	61	80040	6	1	39	43	0	0	1	1	1	5118	0	16	0	0	26724	0	0	14	7	80000	100	26708	26732	26732	26728	26732
80204	26731	200	0	0	0	1	0	67	0	0	0	2	26721	2	7	0	19	25	80100	100	80000	100	80016	500	1168293	1	49	23668	26707	26731	16655	6	16683	80113	200	80024	200	160048	26731	77	1	1	80201	100	99	0	100	80000	100	80000	100	80020	22	43	80059	1	1	0	60	80040	6	1	0	44	0	0	1	1	1	5118	0	16	0	0	26728	0	14	0	7	80000	100	26732	26708	26728	26728	26732
80204	26731	200	0	0	0	0	0	0	0	0	0	1	26692	2	12	1	19	25	80100	100	80000	100	80015	500	1166596	1	49	23627	26707	26707	16635	6	16659	80115	200	80024	200	160048	26731	56	1	1	80201	100	99	0	100	80000	100	80000	100	80020	19	43	80059	0	0	0	21	80039	6	1	0	44	0	0	1	1	1	5118	0	16	0	0	26724	0	10	14	0	80000	100	26732	26732	26708	26732	27003
80204	26741	200	0	0	0	0	0	44	1	0	0	1	26716	2	0	1	19	25	80100	100	80000	100	80015	500	1167198	1	49	23651	26707	26731	16659	6	16683	80115	200	80024	200	160048	26710	77	1	1	80201	100	99	0	100	80000	100	80000	100	80019	19	0	80059	1	1	1	67	80040	6	1	61	43	19	0	1	1	1	5118	0	16	0	0	26711	0	13	13	0	80000	100	26737	26715	26737	26737	26715
80204	26737	200	1	0	1	0	0	45	1	0	0	1	26720	0	1	12	79	25	80100	100	80000	100	80015	500	1166596	1	49	23949	27035	26707	16659	6	16661	80114	200	80024	200	160048	26883	77	1	1	80201	100	99	0	100	80000	100	80000	100	80019	20	0	80058	1	0	1	60	80040	6	1	19	43	19	0	1	1	1	5118	0	16	0	0	26733	0	13	0	5	80000	100	26741	26737	26737	26737	26737
80204	26736	200	1	0	1	1	1	44	0	0	0	1	26716	0	1	0	19	49	80100	100	80130	100	80015	500	1165620	1	49	23636	26742	26714	16664	6	16666	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	100	80021	20	43	80059	0	1	0	64	80039	6	1	0	44	0	0	1	1	1	5118	0	16	0	0	26728	0	14	14	4	80000	100	26732	26728	26728	26732	26732
80204	26731	200	0	0	0	1	1	21	1	0	0	0	26722	0	7	0	20	25	80100	100	80000	100	80015	500	1166836	1	49	23651	26731	26712	16663	6	16687	80115	200	80024	200	160048	26731	77	1	1	80201	100	99	0	100	80000	100	80000	100	80019	20	43	80059	0	0	0	64	80000	6	1	19	43	19	1	1	1	1	5118	0	16	0	0	26716	0	13	13	5	80000	100	26737	26737	26715	26737	26715
80204	26736	200	1	1	0	0	0	12	0	0	0	0	26716	2	1	1	0	25	80100	100	80000	100	80013	500	1167198	1	49	23657	26714	26736	16644	6	16666	80291	200	80221	200	160048	26740	85	2	1	80201	100	99	0	100	80000	100	80000	100	80019	20	43	80019	0	0	0	60	80040	6	1	59	43	19	1	1	1	1	5143	0	16	0	0	26913	1	13	0	0	80000	100	26737	26738	26738	26741	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	1	45	1	2	26693	2	18	12	12	25	80010	10	80000	10	80000	50	1168843	1	0	49	23648	26708	26727	16672	3	16708	80010	20	80000	20	160000	26727	72	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80035	0	35	80000	6	1	35	0	0	5020	0	0	7	16	7	5	26719	0	10	6	0	80000	10	26709	26709	26728	26709	26709
80024	26728	200	0	0	0	0	1	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1166896	0	0	49	23628	26728	26708	16672	3	16708	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80039	0	39	80039	6	1	39	39	0	5020	0	0	8	16	7	7	26719	0	6	6	2	80000	10	26723	26728	26709	26709	26723
80024	26708	200	0	0	41	0	0	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1166750	0	0	49	23628	26727	26728	16672	3	16707	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80039	0	35	80000	0	1	35	39	0	5020	0	0	5	16	8	7	26705	0	0	6	4	80000	10	26729	26709	26728	26728	26723
80024	26708	200	0	0	0	1	1	26707	2	18	18	12	25	80010	10	80130	10	80000	50	1167605	0	0	49	23642	26728	26727	16672	3	16702	80010	20	80000	20	160000	26725	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	35	80039	6	0	35	43	0	5020	0	0	7	16	5	5	26719	0	6	6	2	80000	10	26728	26728	26728	26728	26709
80024	26727	199	0	0	45	0	2	26693	2	12	12	5	25	80010	10	80000	10	80000	50	1168843	1	0	49	23628	26727	26727	16672	3	16707	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	39	80000	0	1	35	43	0	5020	0	0	7	16	7	8	26719	0	10	6	0	80000	10	26712	26729	26729	26709	26728
80024	26708	200	0	0	45	1	2	26707	0	18	12	12	25	80010	10	80000	10	80000	50	1166993	1	0	49	23628	26728	26722	16667	3	16707	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	39	80039	6	1	0	39	0	5020	0	0	7	16	5	5	26725	0	10	6	2	80000	10	26723	26728	26728	26709	26729
80024	26728	200	0	0	41	1	2	26707	2	12	0	16	25	80010	10	80000	10	80000	50	1166886	1	0	49	23628	26728	26728	16672	3	16707	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	35	80039	6	1	39	39	0	5020	0	0	4	16	5	9	26705	0	10	10	0	80000	10	26726	26723	26709	26729	26709
80024	26708	200	0	0	45	0	0	26711	2	18	18	0	25	80010	10	80000	10	80000	50	1168843	1	0	49	23648	26708	26708	16672	3	16688	80010	20	80000	20	160000	26741	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	35	80039	6	0	35	43	0	5020	0	0	9	16	7	7	26724	0	0	10	0	80000	10	26723	26728	26729	26729	26723
80024	26728	200	0	0	41	0	2	26707	0	12	0	16	25	80010	10	80000	10	80000	50	1166750	0	0	49	23642	26722	26709	16652	3	16708	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	80039	6	1	39	0	0	5020	0	0	7	16	8	7	26705	0	10	10	2	80000	10	26723	26723	26709	26728	26729
80024	26728	200	0	0	45	0	0	26712	2	18	0	0	25	80010	10	80000	10	80000	50	1172240	0	0	49	23647	26728	26727	16672	3	16702	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	35	80039	6	0	35	0	0	5020	0	0	7	16	5	10	26725	0	0	6	4	80000	10	26729	26728	26728	26728	26729

LDR (register, uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations