Firestorm: NEGS (register, lsl, 32-bit) measurements

Code:

  negs w0, w0, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	1	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	1000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  negs w0, w0, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	1	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10009	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	2	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	10200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	1	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	1	0	640	3	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	251	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	27	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	3	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	10020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs w0, w1, lsl #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20107	20224	20224	30035	85	2	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	4	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	6	1	1	1	1319	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	89	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29987	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	1	0	1	1	1	1320	1	16	1	1	29986	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	124	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	20224	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29987	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	2018	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	9	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	1789	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	631	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	61	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	61	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	1	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	588	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	61	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	1117	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	61	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	61	10000	29891	25	30010	30010	20010	1956289	49	23927	30035	30035	27391	3	27498	20010	20020	20020	30035	85	1	1	20021	10	9	10	20010	10010	0	3	0	0	1270	1	17	2	1	29959	30000	20010	30036	30036	30036	30036	30036

Test 4: throughput

Count: 8

Code:

  negs w0, w8, lsl #17
  negs w1, w8, lsl #17
  negs w2, w8, lsl #17
  negs w3, w8, lsl #17
  negs w4, w8, lsl #17
  negs w5, w8, lsl #17
  negs w6, w8, lsl #17
  negs w7, w8, lsl #17

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53430	400	1	1	0	1	950	80013	48791	29	160137	160137	80176	3441890	1	49	50334	0	53414	53414	43345	3024	8	43355	80176	80288	80288	53414	39	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5126	6	16	8	7	53411	160037	80100	53415	53415	53415	53414	53415
80204	53414	400	1	1	0	1	85	80000	48741	25	160100	160100	80100	3440005	0	49	50446	0	53410	53410	43298	2909	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	4	0	0	0	0	0	5112	9	24	8	7	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	254	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	3024	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5112	8	24	8	7	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	399	1	1	0	1	64	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	3024	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5112	7	24	8	9	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	64	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	3024	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5112	8	24	7	7	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	64	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	3024	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5112	7	24	8	7	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	1031	80000	48741	25	160100	160100	80100	3440005	0	49	50386	0	53410	53410	43298	2909	3	43360	80100	80200	80200	53410	39	1	1	80202	100	99	100	80100	100	0	0	0	0	0	0	0	5112	8	24	7	6	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	64	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	3024	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5112	8	24	8	6	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	64	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	3024	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5112	7	24	7	8	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	1	1	0	1	169	80000	48741	25	160100	160100	80100	3440005	0	49	50330	0	53410	53410	43298	2909	3	43360	80100	80200	80200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5114	8	24	6	6	53390	160000	80100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	53401	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	3251	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	11	24	2	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	3251	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	24	6	2	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53438	53437	43290	2749	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	24	6	2	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	0	53380	53380	43290	3251	3	43352	80010	80020	80112	53380	39	1	1	80021	10	9	10	80010	10	0	1	0	0	0	5020	0	3	24	2	2	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	3	53380	53380	43290	2749	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	6	24	2	2	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	2936	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	24	3	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	2936	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	24	2	2	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	3251	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	24	2	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	3251	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	6	24	2	2	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	49	50300	0	53380	53380	43290	3251	3	43352	80010	80020	80020	53380	39	1	1	80021	10	9	10	80010	10	0	1	0	0	0	5020	0	2	24	2	6	53360	160000	80010	53381	53381	53381	53381	53381

NEGS (register, lsl, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations