Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (OSH)

Test 1: uops

Code:

  dsb osh

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
1004170321279170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321270170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321280170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321270170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321270170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321270170171580110001000101760001491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321280170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170481280170171580110001000100060000491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
1004170321270170171580110001000100060001491395214859170323168901000100017032170321110011000010000073216221683810001703317033170331703317033
10041703212701701715801100010001000600004913952148591703231689010001000170321703211100110000100053073216221683810001703317033170331703317033

Test 2: throughput

Code:

  dsb osh

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4151schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10204170032127400000780170022015970010100100100001001000050059889149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000071001611169838010000100170033170033170033170033170033
1020417003212730000000170180015970010100100100001001002750059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
102041700321274000005910170034015970010100100100001001000050059800149166952151003170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212740000000170022015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212730000000170022015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212740000000170022015970010100100100001001000050059800149166952150988170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212740000000170022015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212730000000170022015970010100100100001001000050059800049166952150939170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212740000000170022015970010100100100001001000050059800149166952151117170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033
1020417003212730000000170022015970010100100100001001000050059800049166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000071011611169838010000100170033170033170033170033170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)031e3a3f414b51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fst unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10024170032131900170017001597861001010100001010000505998049166952149957170032316876210010201000020170032170032111002110910101000010100000006402162216983801000010170033170033170033170033170033
10024170032127390170017001597861001010100001010000505998049166952149957170032316876210019201008120170411170032111002110910101000010100000006402163316983801000010170033170033170033170033170033
10024170032127400170017001597861001010100001010000505998049166952149957170032316876210010201000020170032170032111002110910101000010100000006402163316983801000010170033170033170033170033170033
10024170032127400170017001597861001010100001010000505998049166952150061170032316876210010201000020170032170032111002110910101000010100000006403162216983801000010170033170033170033170033170033
10024170032127300170017001597861001010100001010000505998049166952150024170032316876210010201000020170032170032111002110910101000010100000006403162216983801000010170033170033170033170033170033
10024170032127400170017001597861001010100001010000505998049166952149957170032316876210010201000020170032170032111002110910101000010100000006402162216983811000010170033170033170033170033170033
10024170032127300170017001597861001010100001010000505998049166952149957170032316876210023201000020170032170032111002110910101000010100000006403163316983801000010170033170033170033170033170033
10024170032127400170034001597861001010100001010000505998049166952149957170032316876210010201000020170032170032111002110910101000010100000006403163316983801000010170033170033170049170033170033
10024170032127400170017001597861001010100001010000505998049166952149957170032316876210010201000020170032170032111002110910101000010100000006403162216983801000010170033170033170033170033170033
10024170032127300170017001597861001010100001010000505998049166952150180170032316876210010201000020170032170032111002110910101000010100000006403163316983801000010170033170033170033170033170033