Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (register, 32-bit)

Test 1: uops

Code:

  orr w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103570618622510001000100016916110351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103583618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580828622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
10041035724618622510001000100016916110351035728386810001000200010354111100110001073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004108070618622510001000100016916110351035728386810001000200010354111100110000073141119371000100010361036103610361036
10041035801038622510001000100016916110351035728386810001000200010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  orr w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035760000270061987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071023711994110000101001003610036100361003610036
102041003575000000061987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
1020410035750000000758987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
102041003575000000061987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
102041003575000000061987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000003071013711994110000101001003610036100361003610036
1020410035750000000736987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
102041003575000000061987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
102041003575000000061987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
102041003575000046800126987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036
1020410035750000000672987725101001010010100886641496955100351003585800387221010010200202001003541111020110099100101001000000000071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575000000014798632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
100241003575000000014998632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
10024100357500000006198632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
10024100357500000006198632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
100241003575000000012698632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
10024100357500000006198632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
100241003575000000053698632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
10024100357500000006198632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
10024100357500000008298632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101000000064024122994010000100101003610036100361003610036
100241003575000000061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000087064024122994010000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  orr w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03091e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035750010398772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750012698772510100101001010088664496955100351003585808872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575036198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711996110000101001003610036100361003610036
10204100357502528998772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357502406198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750081987725101001010010100886644969551003510035858038722101001020020200100354111102011009910010100100001001171013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357500619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100064044155994010000100101003610036100361003610036
10024100357500849863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064064165994010000100101003610036100361003610036
100241003575004799863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064064155994010000100101003610036100361003610036
10024100357600619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064064165994010000100101007210036100361003610036
1002410035750047998632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101001264054155994010000100101003610036100361003610036
10024100357600619863251001010010100108878404969551003510035860278740100101002020020100354111100211091010010100064054144994010000100101003610036100361003610036
10024100357500619863251001010010100108878404969551003510035860238740100101022420020100354111100211091010010100064064155994010000100101003610036100361003610036
10024100357500829863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064054165994010000100101003610036100361003610036
10024100357500619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100064064165994010000100101003610036100361003610036
10024100357500619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100064064164994010000100101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  orr w0, w8, w9
  orr w1, w8, w9
  orr w2, w8, w9
  orr w3, w8, w9
  orr w4, w8, w9
  orr w5, w8, w9
  orr w6, w8, w9
  orr w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413419101034222580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001000511810191091338380000801001338713387133871338713387
80204133861000347258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100051184199101338380000801001338713387133871338713387
8020413386100034225801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005116919991338380000801001338713387133871338713387
80204133861000342258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100051189199101338380000801001338713387133871338713387
802041338610003422580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001000511891910101338380000801001338713387133871338713387
80204133861001834225801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005118919991338380000801001338713387133871338713387
8020413386100813422580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001000511691910111338380000801001338713387133871338713387
80204133861000342258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100051181019791338380000801001338713387133871338713387
8020413386100034225801008010080100400500149103061338613386332333341801008020016020013386391180201100991008010010005118919491338380000801001338713387133871338713387
8020413386100034225801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005118919971338380000801001338713387133871338713387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002413387100100258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100050200319321336880000800101337213372133721337213372
800241337110035258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100050200219241336880000800101337213372133721337213372
800241337110056258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100050200219321336880000800101337213372133721337213372
800241337110035258001080010800104000500491029113371133713330333488001080020160020133713911800211091080010100050200219221336880000800101337213372133721337213372
8002413371100510258001080010800104000500491029113371133713330333488001080020160020133713911800211091080010100050200319331336880000800101337213372133721337213372
800241337110035258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100650200219221336880000800101337213372133721337213372
800241337110035258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010103350200219221336880000800101337213372133721337213372
8002413371100552258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100050200219221336880000800101337213372133721337213372
800241337110035258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100050200319221336880000800101337213372133721337213372
8002413371100982580010800108001040005014910291133711337133303334880010800201600201337139118002110910800101032050200219231336880000800101337213372133721337213372