Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CASL (32-bit)

Test 1: uops

Code:

  casl w0, w1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 4.001

Issues: 3.006

Integer unit issues: 0.000

Load/store unit issues: 3.006

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)0e0f18191e1f22243a3f43464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f63696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafatomic or exclusive succ (b3)atomic or exclusive fail (b4)bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
74007341432569151110001007200528034023202220663009300630092299691493104033664341648253006100230091003601233997270821710011000100003013465100520080078301199913200321505910586279553674173239073685444317655233163190491645217840300010013407534144342813409234085
74005340432562101000001006200539334052203220963006300930092296521493104933680341258263009100230061002601834037268921710011000100003014464100620060115300899913212321509510642281133574064238993591444216726633014186931662617789300010013409934156341603417534123
7400534254256300000000100101052523395111222087300930093009229708149309793368034169725300610033006100360123405627342171001100010001300606310042004901300799911012001517010899080363596263238093668444914626132941189931617617759300010013406034156340993424234128
7400534093255301000000100400053143398310122085300630063006229553149311193357234156726300910023006100260183405027152171001100010000300604410032006902300799911010001504510810079513635267238013516444021605733008190471660817770300010013413334115340973402634067
740053412125550001000010040005285339651102196230093006300622925414931041337463418472630091002300610036012341532722217100110001000030060031004200650107300799911010001560510581279553542260239853629445819586132982191031666617520300010013428834070341203412934077
7400534034254400000000100100053863397810022012300630033009228478149310123366934244825300910023006100360123408227812171001100010000300604410042004206300799911012001560110572179583662467238193556443821626433183187891635617371300010013406534106342443415934132
74005341332565000000001004000539033934101220993009300930092298141493103233735341678253006100230061002601234051271521710011000100003009040100420061105301099911000001502710511080483575156238483674444718627033224188801642717619300010013412934055340713421334078
7400534074255300000000100400054303394011022016300330063009228284149309783365734181726300610033006100260123400127072171001100010000300606310032006270530109991100200154351084418118367215923928359944578727033082188161649917561300010013420834135340743419534053
74005341552557010000001004000550033904101219403006300630062293011493119133693341467263006100230061002601234096274321710011000100003006003100420041205300799911012001498210694179443636063237463597443410585732941189861634817723300010013418634160341213416634096
7400534041256501001100100400054463402910022123300630063006229313149310663371934090826300910023009100360123411527642171001100010000300900310042004902300799912012001498610992480753628264237223687445616627133004187061624117727300010013413734109340903409034165

Test 2: throughput

Code:

  casl w0, w1, [x6]
  add x6, x6, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0065

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0f181e1f202224293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafatomic or exclusive succ (b3)atomic or exclusive fail (b4)b6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c3branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
5021070065525000000534121882001104700501382534246935254010010100300001010130000505553314861149669857003370065596737600424010120203300062020360018700657511202011009901001000010100100000100302310411861390110322200452119005214430261999822962130330011111317016006991810000101030000201007006670066700667006670066
502047006552400000053222191200188700501361383047129254010010100300001010130000505553315352049669867003770065596737600414010120203300062020360000700657711202011009901001000010100100000100302520341751384710381200261420203015030262999822862102330000001310117116990910000101030000201007006670066700667006670066
5020470065525000000526511902002164700501801355147011254010010100300001010030000505533316016049669857003370065596613600474010020200300002020060000700657511202011009901001000010100100000100301990511881388110332200351919305412630260999822582126330040001310117106990910000101030000201007006670066700667006670066
5020470065525110000522622372001687005014613634472132540100101003000010100300005055333153430496698570037700655966036004740100202003000020200600007006575112020110099010010000101001000001003024733622813870103862005726209042192302939998227921243312150001310117116990910000101030000201007006670066700667006670066
5020470065524100100529121952002116700501643415347418254010010100300001010030000505533314629149669857003770065596603600474010020200300002020060000700657311202011009901001000010100100000100301512361981409310353200362317406217930247999822621113331140001310117116990910000101030000201007006670066700667006670066
502047006552511010053332169200114070050162140614772625401001010030000101003000050554331447314966985700337006559661360047401002020030000202006000070065761120201100990100100001010010000210030210278215144611033920055241650611430225999822592100321000001310117116990910000101030000201007006770066700667006670066
5020470065525110100525921852010410700501621443047058254010010100300001010030000505533314491149669867003370065596613600474010020200300002020060000700657511202011009901001000010100100000100301612372041446010331200671817808416330334999821712126321100001310117116990910000101030000201007006670066700667006670066
5020470065525100100528821802001967005014813447470572540100101003000010100300005055333151501496698570034700655966136004740100202003000020200600007006575112020110099010010000101001000001003019814419213523103672005127209094146302499998221012119631130001310117116990910000101030000201007006670066700667006670066
502047006552510100053103162200184700501941303846799254010010100300001010030000505533314670149669857003870065596603600474010020200300002020060000700657511202011009901001000010100100000100302302431721387010402200486026508214530278999822542105331000001310117116990910000101030000201007006670066700667006670066
5020470065525101000525212102032168700501825373446669254010010100300001010030000505543314149149669857003770065596613600474010020200300002020060000700657311202011009901001000010100100000100302522412111367510402200405121601201693024599982367280331020001310117116990910000101030000201007006670066700667006670068

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0061

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafatomic or exclusive succ (b3)atomic or exclusive fail (b4)b6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
5003070065525000010105223214610016811007587522113745553133794252810928310501087833213585783897934014979194086780865507168913872437451932200832007220026858081124751712002110910478101000010010100000103228924217621280111722104514212028114566321339998235531016324157351851068235210922101030000200107006770066700667006670658
5002470068610301110181488932024169100017675300195139295679937143034111983220510658326015596638289431049669850706217297563154537195743117223303313522554669307967976211200211098677101000010010100000103272444216424811112222131831249050102719318139998225621193302165492514469909110261021530000200108285384574868908397982851
500248109663300000100572710591660011922807585017213326587216034430911475326251136033888575583958967004966985070033729836569212600374001020020300002002060330700617111200211090101000010010100000103023303918513197103292004128028532193303589998201203164260012704174469905100006630000200107006270062700627006270065
500247006152500000000532251940010116070046145237344681125400101001030000100103000050104331532610496396007003370061596573600434001020020300002002060000700617411200211090101000010010100000103017703216813868102922006329225026178302569998201042109500212702174469905100006730000200107006270062700627006370062
5002470061525000000005271417400181527004613633727474782540010100103000010010300005010233142421049669810700297006159647360043400102002030000200206034270061711120021109010100001001010000010302070323161354310282200411525104012530239999820733120260212704174469905100006630000200107006270062700627006270053
50024700615250000000051653111001168651607004615723934476582540010100103000010010300005010433148310049669810700247006159656360043400102013530000200206000070061711120021109010100001001010000010301470383021359610252200542218304415130349999820643122250712705174469905100006630000200107006270062700627006470062
50024700615240000110052324178001136156700462212294047854254001010010300001001030000501043314924004966981070029700615965736004340010200203000020020600007006171112002110901010000100101000001030184041335139061026820049233187681273025699982082375260112704172469905100006630000200107006270062700627006270053
500247006152500000000529032020010172700461862353546999112400101001030000100103000050104331446300496698107002970061596563600434001020020300002002060000700617111200211090101000010010100000103017303425113647102792006115229026172302329998208710100260412704174569906100006630000200107006270053700627007270062
50024700615240000000053034132001011207004621102350471912540010100103000010010300005010433140190049669810700207006159657360043400102002030000200206000070061701120021109010100001001010000010301150382721367410234200581725703015730240999820913109260012704174469905100006630000200107006270062700627006370062
500247006152400000000518042140101684168700371794404147188254001010010300001001030000501033315333004966985070037700655966436004740010200203000020135600007006575112002110901010000100101000001030208057228140521018920046142330241673023199982273213663601270417446990910000101030000200107006670075700727006670066

Test 3: throughput

Code:

  casl w0, w1, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0104

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)606367696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafatomic or exclusive succ (b3)atomic or exclusive fail (b4)bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2st memory order violation nonspec (c4)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d1d2d5map dispatch bubble (d6)daddfetch restart (de)e0e2e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
41846701045250000000015234000020700880109674510837433643534317738210947515591669368110496702470080701047075119382263411335489021202542008124662419522360947010570105211020110099100100001001000011004169102815113072932721432008062502259999182982120029250242144906027338002522700113586006630000116267010470105701057010570105
4170870104525000000001536521000700891118896510605428423874225238711259114561733925110496737572017701105235116592373411323183061268141333121086425262492947009470105211020110099100100001001000011004163102812114232789121389009566490179999181082120029831142174209023313402829700203401006630000116087010670105700957010570096
41708701045250000000014428210007008801387535107944418639842816370110599193317149601104967024700787010459031191622772113517857512108425011240984175624550870104701042110201100991001000010010000010042880028141117928137214321010418492459999186512120031251032106000028304202428700083389216030000116197010570107701047010570109
418007010452500000000149072100170089013868989977446693824386249211059619761724704110496702370077701056507117592488411078786891237841866124029421732423407009470103211020110099100100001001000001004265202814112772946921922109633482139999179192120030660162130208027347802833700103424006630000116507010570105701057010570104
41799701045250000000015008210007007901086952108404331840143566412111440213317315011104967023700797010457951176823699113888847811979420631210084161824369670104701042110201100991001000010010000010042193028141108527261214500010051485749999186060120031060142131700033374302321700313484206030000116647010570105701057010570105
4172970104525000000001465321000700881108697410383440633944408940811208921371696366010496702470857701035300122382397511094382981232141277123162421312425567010470103211020110099100100001001000001004246502814115232639621302609217477029999185260120031031022185914024319902529700183380006630000116447010570106701057011070105
417107010452500000000144552100207008901178219114484428736342418404112005153517421421104967025700707010465411198725400113094934613524416021206904229323402470107701052110201100991001000010010000010043111028161102728837215280010280489009999176922120033661142116806029322602429700173434106630000116097010870105701057010570106
4174270104525000000001430720000700901108775510342438034184387439611088721101713522110496702470078701046513120502216911405186601233742202125034421912476927010470104211020110099100100001001000001004250600151091430122215860010271509939999183952100029750042144308028310202931700103417346630000116617010470095701057010570105
4175070104525000000001504621000700891121173941115944111397424453791126951852171152801049670247007670103610911849232271115318863127384117912307842320245928701057010521102011009910010000100100000100407390281311040294682144600948250850999918960212003178115210660802324402523700193496206630000116337010670105701057010570105
4178470109525000000001371121000700892138733710130438664054302831311083419851703664010496701470082701076431121272348611309290141220342044120588422932476447010470105211020110099100100001001000001004261300151125827347212561092984835499991864621200310211521335110029336302730700143428006630000116947010570104701147011670105

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0110

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6063696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafatomic or exclusive succ (b3)atomic or exclusive fail (b4)bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)st memory order violation nonspec (c4)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e2e7eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
416897010452510200021865200070079208241012597514004451495431277152121514765114967039070084700949241343615504127812427533449161344964489726903470117701102110021109010100001010000110507843408964404712330001713763762999911603821225300223227244584283670004402036630000116767009570095701177009570111
41681700945256050002220200007008827724621259851464505124950127690250152332901496701407006970094102913462156971276725496984493813427144886269010701107009421100211090101000010100001105077834091854110423288017627641679999115688002255802219813274506303770004414830930000116677011170118701187011870095
41689701105254020002186620007008028823901256851712415135444127725250151877801496702407008570105919133961564612781838669444918134304448502687707009470107211002110901010000101000011050878341691824107123254017491637479999115747010253302211310374474393770023415036630000116737011870118701067009570095
4168170107525103000221990000700952772350125835151640515674712770421015170480149670380700937011092713414155301277404917344490213446044928268980700947011021100211090101000010100000105088028169136408992330401727464304999911591621225170220769394488333070024414236930000116757009570095701117010970118
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