Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CRC32CB

Test 1: uops

Code:

  crc32cb w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004303322103192225100010001000814400403033303327603289110001000200030333801110011000010731161129391000100030343034303430343034
100430332382192225100010001000814401403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
1004303323126192225100010001000814400403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
1004303323109192225100010001000814401403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
100430332261192225100010001000814401403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
100430332361192225100010001000814400403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
1004303323103192225100010001000814400403033303327603289110001000200030333801110011000050731161129391000100030343034303430343034
1004303323103192225100010001000814401403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
100430332261192225100010001000814401403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034
1004303323147192225100010001000814400403033303327603289110001000200030333801110011000000731161129391000100030343034303430343034

Test 2: Latency 1->2

Code:

  crc32cb w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204300332246119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332246119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101438289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332246119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332256119922251010010100101008289404926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250012419922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
1002430033225006119922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
10024300332250061199222510018100101001082849049269530300333003328632328763100101002020020300333801110021109101001010002700640216222993910000100103003430034300343003430034
10024300332250316819922251001010010100108284904926953330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
10024300332241020419922251001010010100108284904926953030033300332863232876310010100692002030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322500124619922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
10024300332250029519922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
1002430033224008419922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
1002430033225008419922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
1002430033225008419922251001010010100108284904926953030033300332863232876310010100202002030033380111002110910100101002000640216222993910000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  crc32cb w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)0318191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322400061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010020710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200302083741110201100991001010010013712116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500061199222510100101001010082894014926953300333003328610328741101001020020200300333741110201100991001010010000710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002430033224017019922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640217222993910000100103003430034300343003430034
100243003322508219922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
1002430033225010319922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101001640216222993910000100103003430034300343003430034
100243003322508419922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
1002430033225012619922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
1002430033225020419922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322508219922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250517719922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322509119922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
1002430033225058719922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034

Test 4: throughput

Count: 8

Code:

  crc32cb w0, w8, w9
  crc32cb w1, w8, w9
  crc32cb w2, w8, w9
  crc32cb w3, w8, w9
  crc32cb w4, w8, w9
  crc32cb w5, w8, w9
  crc32cb w6, w8, w9
  crc32cb w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204800376000000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000000005110316228003180000801008003680036800368003680036
80204800355990000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800356000000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800355990000462580100801008010040050004976309080035800356996436999380100803331602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800355990000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800355990000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800355990060462580100801008010040050004976955080035800356996436999380100802001602008003533711802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800355990000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
80204800356000000462580100801008010040050004976955080035800356996436999380100802001602008003516411802011009910080100100000100005110216228003180000801008003680036800368003680036
80204800355990000462580100801008010040050014976955080035800356996436999380132802001602008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cdcfd0d5map dispatch bubble (d6)dadbddfetch restart (de)e0? int output thing (e9)eaec? int retires (ef)f5f6f7f8fd
800248003559900002382580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000000502005160029800328000000800108003680036800368003680036
800248003559900007112580010800108001040005001497695538003580035699863700158001080020160020800351641180021109108001010003000502004160044800328000000800108003680126800368003680036
800248003559900005212580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000000502004160055800328000000800108003680036800368003680036
8002480035600000071125800108001080010400050004976955080035800356998637001580010800201600208003516411800211091080010100000005020041600438003280000018800108007580036800368003680036
800248003560000007112580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000000502003163043800328000000800108003680036800368003680036
800248003559900007112580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000000502004160033800328000000800108003680036800368003680036
800248003559900007112580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000010502003160055800328000000800108003680036800368003680036
80024800356000000882580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000000502005160055800328008500800108003680036800368003680036
800248003559901200882580010800108001040016201497695508003580035699863700158001080020160020800351641180021109108001010000000502003160043800328000000800108003680036800368003680036
8002480035599093520462580010800108001040005001497695508003580035699863700158001080020160020800351641180021109108001010000000502005160055800328000000800108003680036800368003680036