Firestorm: SUBS (register, 64-bit) measurements

Code:

  subs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	82	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	416	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	42	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	57	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  subs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	103	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	3	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	108	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	145	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	4	111	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	4	78	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	2287	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	1	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	18	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	3	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	9	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	18	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	1	3	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	3	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	66	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	768	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	1	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	6	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  subs x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9927	25	10100	10100	10110	647212	1	49	6955	10035	10035	8673	8	8735	10110	10224	20248	10035	40	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	10013	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10100	10100	10110	647212	1	49	6955	10035	10035	8673	8	8735	10110	10224	20248	10035	40	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	10013	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10100	10100	10110	647212	1	49	6955	10035	10035	8673	8	8735	10110	10224	20248	10035	40	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	10013	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	147	9927	25	10100	10100	10110	647212	1	49	6955	10035	10035	8673	8	8735	10110	10224	20248	10035	40	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	10012	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10100	10100	10110	647212	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	124	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10191	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	84	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	1	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	145	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10083	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	15	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	168	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	1	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	124	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20354	157	0	1	0	8	801	616	82	19930	65	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17587	20112	20224	31229	20035	64	1	1	20201	100	99	100	20100	10100	0	2	0	1	0	0	0	1	1	1	1319	1	24	2	2	20114	20000	20100	20400	20266	20036	20036	20446
20204	20035	156	0	0	0	0	9	0	82	19930	235	20100	20100	20112	1297233	1	49	16955	20171	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	0	1605	0	1	1	1	1337	4	40	1	1	20114	20000	20100	20081	20493	20036	20036	20535
20204	20035	150	0	0	0	5	9	0	82	19930	212	20100	20100	20112	1297936	1	49	16955	20035	20035	17477	8	17486	20441	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	2	16	1	1	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	2	16	1	1	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	61	19924	168	20258	20169	20606	1300333	1	49	17229	20307	20312	17486	45	17637	20112	20796	31234	20310	64	2	1	20201	100	99	100	20100	10100	0	2	0	0	0	5453	0	1	1	1	1419	4	56	1	2	20217	20133	20100	20306	20313	20310	20356	20309
20204	20126	153	1	0	7	6	924	616	851	19926	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20192	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	3	0	1	1	1	1319	2	16	1	1	20149	20112	20100	20264	20266	20081	20217	20264
20204	20081	151	0	0	5	1	660	88	61	19930	25	20100	20100	20112	1297233	1	49	17230	20307	20035	17425	25	17564	20112	20224	30236	20080	64	2	1	20201	100	99	100	20100	10100	0	4	2	1	0	0	0	1	1	1	1387	4	50	1	1	20150	20089	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	61	19927	89	20237	20190	20445	1299738	1	49	17183	20263	20035	17473	30	17615	20442	20694	31101	20311	64	6	1	20201	100	99	100	20100	10100	0	0	0	0	0	3	0	1	1	1	1319	3	66	1	2	20012	20000	20100	20082	20082	20036	20081	20081
20204	20035	152	0	0	6	6	801	528	346	19928	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20793	31096	20080	64	8	1	20201	100	99	100	20100	10100	2	2	4	0	4	4790	2	1	1	1	1402	2	16	1	1	20044	20069	20100	20354	20172	20454	20398	20493
20204	20261	164	0	0	0	0	0	0	1244	19930	151	20330	20237	20112	1297233	1	49	17319	20491	20443	17522	45	17739	20946	21188	31676	20492	64	11	1	20201	100	99	100	20100	10100	0	0	0	0	2	8585	0	1	1	1	1319	1	16	1	1	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	4	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	191	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	9	132	255	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	191	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	1	0	1270	2	27	2	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	84	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	126	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	170	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	1339	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	9	0	493	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	3	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	6	16	3	4	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	542	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	3	16	3	5	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	1	16	3	4	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	2	16	3	4	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1321	5	16	3	4	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1321	2	16	4	5	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	2	16	4	4	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1321	5	16	4	5	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	9	1	67	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	2	16	2	3	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	2	0	2	0	0	0	1	67	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	5	16	4	4	20015	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	0	0	0	203	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	2	0	0	0	0	0	1270	3	27	7	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	149	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	3	27	7	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	212	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	2	0	0	1270	3	27	6	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	354	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1	1270	3	27	5	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	3	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	2	27	6	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1	0	0	0	0	0	1270	3	27	3	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	2	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	455	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	2	0	0	0	0	1270	3	27	6	3	19995	20022	20010	20080	20081	20036	20036	20036
20024	20035	150	0	1	0	0	0	0	0	0	0	483	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	3	27	6	4	20030	20044	20010	20036	20036	20036	20127	20082

Test 6: throughput

Count: 8

Code:

  subs x0, x8, x9
  subs x1, x8, x9
  subs x2, x8, x9
  subs x3, x8, x9
  subs x4, x8, x9
  subs x5, x8, x9
  subs x6, x8, x9
  subs x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26762	201	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16708	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26783	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	9	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	9	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	26722	200	0	0	0	77	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	15	18	0	18	15	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	121	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	1	0	3	5020	9	18	0	11	12	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	14	18	0	7	8	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	7	18	0	16	9	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	12	18	0	12	6	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	1	0	0	0	0	5020	12	18	0	9	9	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	10	18	0	19	10	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	605	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	6	18	0	8	9	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	510	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	12	18	0	6	8	26702	80000	0	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	7	18	0	20	8	26702	80000	0	80010	26706	26706	26706	26706	26706

SUBS (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations