Firestorm: STR (register, sxtw, 64-bit) measurements

Code:

  str x0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	554	4	0	7	0	527	16	16	0	25	1000	1000	1000	22352	1	540	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	0	1000	0	2	1002	2	42	73	1	16	1	1	540	1000	541	541	543	543	541
1004	543	4	0	3	1	528	16	16	0	25	1000	1000	1000	22352	1	540	543	356	3	398	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	1002	2	42	73	1	16	1	1	539	1000	543	541	541	543	543
1004	542	4	6	3	0	525	0	16	1	25	1000	1000	1000	22472	1	543	540	353	3	400	1000	1000	3000	540	543	1	1	1001	1000	1000	1000	0	0	1002	0	2	1002	2	0	73	1	16	1	1	539	1000	543	543	541	555	541
1004	542	4	0	0	1	527	0	16	1	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	0	1000	1	0	1000	2	42	73	1	16	1	1	539	1000	543	541	541	543	543
1004	540	4	6	0	0	525	0	16	0	25	1000	1000	1000	22448	1	540	554	355	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	0	73	1	16	1	1	540	1000	544	541	544	544	541
1004	540	4	0	3	0	525	0	0	0	25	1000	1000	1000	22448	1	542	540	353	3	398	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	42	0	1000	0	5	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22448	1	542	540	355	3	412	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	1000	0	42	73	1	16	1	1	539	1000	543	543	541	541	544
1004	540	4	0	3	0	528	0	16	0	25	1000	1000	1000	22448	1	542	542	353	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	0	0	1002	0	2	1000	0	42	73	1	16	1	1	539	1000	543	541	543	544	543
1004	542	4	0	3	0	528	16	16	1	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	0	1	1002	0	0	1002	0	0	73	1	16	1	1	539	1000	541	543	543	543	541
1004	542	4	0	3	1	525	16	0	0	25	1000	1000	1000	22352	1	540	542	355	3	401	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	42	0	1000	0	2	1002	2	42	73	1	16	1	1	539	1000	555	543	543	543	541

Count: 8

Code:

  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]
  str x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40052	300	1	1	1	0	0	0	19	1	0	0	1	40037	16	0	2	25	80100	100	80000	100	80006	500	1839987	1	49	36967	40052	40053	29971	7	30005	80106	200	80016	200	240048	40054	32001	1	1	80201	100	99	100	80000	100	80000	100	80015	14	44	0	0	80016	0	1	17	80002	14	0	14	0	1	1	1	5118	0	16	0	40039	80000	100	40043	40043	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	3	1	0	0	0	40027	16	16	1	25	80100	100	80000	100	80006	500	1840031	1	49	36962	40042	40054	29961	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80002	0	0	2	80000	2	42	0	0	1	1	1	5118	0	16	0	40039	80000	100	40044	40043	40043	40044	40043
80204	40040	300	0	0	0	0	0	0	3	0	0	0	0	40025	16	16	1	25	80100	100	80000	100	80006	500	1839474	1	49	36962	40042	40040	29959	7	29994	80106	200	80016	200	240048	40043	40179	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	1	1	1	5118	0	16	0	40039	80000	100	40044	40044	40043	40041	40043
80204	40042	300	0	0	0	0	0	0	3	1	0	0	1	40048	16	16	1	25	80100	100	80000	100	80007	500	1840035	1	49	36983	40054	40047	29974	7	29999	80106	200	80016	200	240048	40053	32007	1	1	80201	100	99	100	80000	100	80000	100	80014	14	44	0	1	80016	0	1	24	80002	16	44	14	0	1	1	1	5118	0	16	0	40060	80000	100	40055	40054	40055	40055	40055
80204	40052	300	1	1	1	0	0	0	14	1	0	0	1	40039	0	16	5	25	80100	100	80000	100	80006	500	1839959	1	49	36967	40047	40052	29982	7	30005	80107	200	80016	200	240048	40054	32016	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	0	1	80016	0	0	18	80002	14	44	14	1	1	1	1	5118	0	16	0	40049	80000	100	40048	40055	40065	40055	40055
80204	40054	300	1	1	0	0	0	81	20	1	0	0	1	40039	0	16	3	25	80100	100	80000	100	80006	500	1839939	1	49	36972	40063	40051	30022	7	30006	80106	200	80016	200	240048	40053	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	14	44	0	2	80016	0	2	17	80000	16	44	14	2	1	1	1	5118	0	16	0	40051	80000	100	40055	40053	40048	40053	40055
80204	40047	299	1	1	1	0	0	69	17	1	0	0	1	40048	16	16	1	25	80100	100	80000	100	80007	500	1840035	1	49	36968	40054	40054	29974	7	30015	80107	200	80016	200	240048	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	14	44	0	1	80014	0	1	19	80002	16	44	14	1	1	1	1	5118	0	16	0	40051	80000	100	40048	40049	40055	40053	40055
80204	40064	300	1	1	0	0	0	63	18	1	0	0	1	40038	16	16	0	25	80100	100	80000	100	80007	500	1840054	1	49	36984	40054	40054	29966	18	30015	80107	200	80016	200	240048	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	1	80014	0	1	19	80002	16	0	14	2	1	1	1	5118	0	16	0	40049	80000	100	40048	40055	40064	40055	40055
80204	40053	300	1	0	1	0	0	84	20	1	0	0	1	40032	16	0	5	25	80100	100	80000	100	80006	500	1839960	1	49	36972	40047	40048	29983	7	30004	80106	200	80016	200	240048	40047	32017	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	0	80016	0	1	17	80002	16	44	14	1	1	1	1	5118	0	16	0	40060	80000	100	40055	40053	40048	40052	40055
80204	40063	300	1	1	1	0	0	111	21	1	0	0	1	40039	16	16	6	25	80100	100	80000	100	80007	500	1840054	1	49	36984	40054	40054	29973	7	30006	80106	200	80016	200	240048	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80016	15	0	0	2	80016	0	1	17	80002	16	44	14	2	1	1	1	5118	0	16	0	40049	80000	100	40053	40055	40048	40048	40064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40059	299	1	1	0	1	24	3	1	0	0	0	40032	16	16	5	25	80010	10	80000	10	80000	50	1839908	0	1	49	36975	40051	40040	29975	3	30031	80010	20	80000	20	240000	40059	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	1	80002	0	0	0	80002	2	0	14	2	5020	3	16	0	4	4	40049	80000	10	40052	40048	40053	40049	40051
80024	40058	300	1	0	0	1	0	19	0	0	0	1	40042	16	16	2	25	80010	10	80000	10	80000	50	1840220	0	1	49	36979	40059	40059	29993	3	30041	80010	20	80000	20	240000	40059	40059	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	0	0	80016	0	1	14	80002	16	36	14	1	5020	4	16	0	4	4	40047	80000	10	40048	40053	40061	40048	40059
80024	40052	300	1	1	0	0	0	19	0	0	0	1	40044	16	16	11	25	80010	10	80000	10	80000	50	1839692	0	1	49	36967	40052	40058	29994	3	30039	80010	20	80000	20	240000	40052	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	15	0	0	0	80016	0	0	18	80002	14	35	14	0	5020	3	16	0	3	4	40057	80000	10	40059	40053	40058	40054	40060
80024	40052	300	1	1	0	0	81	14	1	0	0	1	40032	16	16	2	25	80010	10	80000	10	80000	50	1839692	0	1	49	36960	40042	40054	29985	3	30020	80010	20	80000	20	240000	40058	40060	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	1	80016	1	1	18	80000	14	36	14	6	5020	4	16	0	4	3	40047	80000	10	40059	40053	40061	40060	40048
80024	40052	300	1	1	1	1	0	18	0	0	0	1	40037	16	16	5	25	80010	10	80000	10	80000	50	1839956	0	1	49	36969	40061	40058	29994	3	30031	80010	20	80000	20	240000	40128	40059	1	1	80021	10	9	10	80000	10	80000	10	80014	14	0	0	1	80076	0	0	21	80002	14	0	14	2	5020	4	16	0	3	4	40044	80000	10	40050	40048	40052	40048	40062
80024	40058	300	1	0	0	0	0	18	1	0	0	1	40045	16	16	6	25	80010	10	80000	10	80000	50	1840221	0	1	49	36982	40059	40059	29993	3	30030	80010	20	80000	20	240000	40059	40059	1	1	80021	10	9	10	80000	10	80000	10	80016	15	36	0	0	80016	1	1	22	80002	14	36	14	0	5020	4	16	0	3	3	40049	80000	10	40061	40059	40050	40060	40060
80024	40058	300	1	0	0	1	6	17	1	0	0	1	40032	16	0	5	25	80010	10	80000	10	80000	50	1840220	0	1	49	36980	40050	40052	29987	3	30027	80010	20	80000	20	240000	40051	40052	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	1	80014	0	1	21	80000	14	36	14	0	5020	3	16	0	3	3	40045	80000	10	40060	40048	40059	40052	40053
80024	40049	300	1	0	1	0	0	0	1	0	0	1	40044	16	16	9	25	80010	10	80000	10	80000	50	1839719	0	1	49	36978	40053	40058	29994	3	30038	80010	20	80000	20	240000	40047	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	1	80016	0	1	14	80002	16	36	14	0	5020	3	16	0	3	4	40056	80000	10	40048	40061	40060	40061	40048
80024	40058	300	1	0	0	1	30	14	1	0	0	1	40034	0	16	5	25	80010	10	80000	10	80000	50	1840244	0	1	49	36983	40601	40052	29987	3	30027	80010	20	80000	20	240000	40052	40052	1	1	80021	10	9	10	80000	10	80000	10	80014	15	0	0	2	80014	1	1	14	80062	14	36	14	2	5020	4	16	0	4	3	40044	80000	10	40059	40048	40060	40048	40060
80024	40051	300	1	1	1	1	0	18	0	0	0	1	40044	16	15	5	25	80010	10	80000	10	80000	50	1840268	0	1	49	36975	40051	40053	29987	3	30038	80010	20	80000	20	240000	40051	40053	1	1	80021	10	9	10	80000	10	80000	10	80015	16	0	0	1	80016	0	0	18	80002	16	36	14	0	5020	4	16	0	4	4	40045	80000	10	40048	40053	40059	40048	40048

STR (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations