Firestorm: AXFLAG measurements

Code:

  axflag

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d tlb miss (a1)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	1035	8	12	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	156	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	156	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	2	27	2	2	990	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->1

Code:

  axflag

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	2	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	648410	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	36	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	76	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	2	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	78	3	84	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	2	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	12	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036

Test 3: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53442	400	45	1	419	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	20	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	3	19	2	3	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	267	1	39	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	2	19	3	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	399	90	1	39	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	3	19	3	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	33	1	39	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	3	19	3	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	48	1	229	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	3	19	3	3	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	399	54	1	39	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	3	19	3	3	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	66	1	704	25	160100	160100	160100	1063588	0	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	2	19	3	3	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	450	1	39	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	3	19	3	3	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	87	1	704	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	2	19	3	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	399	30	1	1482	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160311	80200	53404	66	1	1	160201	100	99	100	80100	100	0	10112	2	19	3	2	53400	160000	100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53391	400	2	402	49	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	3	1	1	24	19	2	1	1	20	19	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	4	0	10022	6	1	1	13	19	2	1	2	13	18	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	18	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	7	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	3	1	1	17	19	4	1	2	19	16	53370	160000	30	17	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	49	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	3	1	2	17	19	4	1	2	17	18	53370	160000	15	17	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	49	25	160010	160069	160010	1029388	0	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10024	6	2	2	17	19	4	2	2	17	17	53370	160000	15	17	10	53375	53411	53375	53375	53375
160024	53374	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	3	1	1	19	19	4	2	2	14	20	53370	160000	30	7	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	292	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	6	2	1	15	19	2	2	1	17	18	53370	160000	30	7	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	49	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10024	6	2	2	16	19	2	2	1	18	16	53370	160000	30	7	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	49	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	6	2	1	16	19	2	2	1	16	16	53370	160000	30	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	234	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	10022	6	2	1	15	19	2	1	1	17	15	53370	160000	30	7	10	53375	53375	53375	53375	53375

Test 4: throughput

Count: 4

Code:

  fcmp s0, s0
  axflag
  axflag
  axflag
  axflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13465	109	0	0	0	0	15	0	0	227	27	83	50785	40194	10124	40810	10200	586083	81154	1	13576	13655	13710	6415	2056	21	7163	50488	40684	10123	40595	20196	13473	13708	2	1	50201	100	99	100	100	10000	100	0	0	0	0	1	2	3580	0	0	0	3210	5	81	2	2	13701	40301	100	13715	13479	13652	13712	13703
50204	13768	106	0	1	5	5	0	440	0	3146	22	162	50781	40625	10194	40899	10168	585704	81560	1	13711	13816	13825	6011	2624	32	7358	50974	40682	10201	40965	20388	13880	13822	6	1	50201	100	99	100	100	10000	100	7	0	3	0	0	0	4100	2	0	0	3357	2	101	2	1	13718	40000	100	13415	13415	13415	13415	13415
50204	13414	104	0	0	6	3	861	528	0	971	15	81	50695	40618	10170	40705	10124	578356	80987	0	13720	13874	13824	6250	2567	40	7388	51096	40987	10197	40982	20346	13887	13884	9	1	50201	100	99	100	100	10000	100	0	0	0	0	0	0	3605	2	0	0	3324	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	104	0	0	0	0	15	0	1	45	0	25	50100	40100	10000	40100	10000	572812	80199	1	13482	13533	13597	5868	2050	12	7190	50367	40499	10050	40404	20100	13534	13541	3	1	50201	100	99	100	100	10000	100	0	0	3	0	0	2	1015	2	0	0	3248	2	36	2	2	13556	40161	100	13415	13415	13415	13415	13478
50204	13474	105	1	1	1	2	144	88	0	456	12	25	50100	40100	10000	40198	10049	590156	80205	1	13441	13477	13536	6128	2456	11	7182	50366	40296	10049	40394	20048	13487	13478	2	1	50201	100	99	100	100	10000	100	0	2	0	0	0	2	1510	0	0	0	3210	4	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	104	0	0	0	0	12	264	0	94	0	25	50100	40100	10000	40100	10025	574757	80000	1	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	0	0	1	0	3	0	0	0	3210	2	19	2	2	13459	40094	100	13415	13415	13415	13415	13415
50204	13414	104	0	0	0	0	3	0	0	66	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6072	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	2	1	50201	100	99	100	100	10000	100	0	0	0	0	2	0	3	0	0	0	3267	2	56	3	4	13553	40378	100	13415	13415	13415	13415	13415
50204	13414	103	0	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6130	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	3	0	0	6	1045	0	0	0	3248	3	36	3	2	13508	40159	100	13537	13539	13593	13530	13539
50204	13535	101	0	0	2	2	315	176	0	293	0	63	50315	40180	10074	40317	10025	564953	80389	1	13385	13471	13477	5887	3048	7	7198	50358	40406	10050	40297	20092	13595	13473	2	1	50201	100	99	100	100	10000	100	2	0	0	0	1	0	505	2	0	0	3246	2	35	3	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	104	0	0	0	0	12	0	0	143	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13408	100	1	0	0	0	66	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	2	0	2	0	1505	3140	6	19	4	5	13379	40000	10	13383	13496	13383	13383	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10025	572032	80191	0	13353	13438	13440	5575	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	4	19	5	4	13379	40000	10	13462	13495	13501	13463	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13440	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	6	19	4	4	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	45	25	50204	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	7	19	4	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	5	19	6	7	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	104	0	0	0	0	129	25	50010	40010	10000	40010	10013	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	4	19	4	4	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	4	19	5	6	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	4	19	5	4	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	0	0	0	3140	4	19	5	4	13379	40000	10	13383	13383	13383	13441	13383
50024	13382	100	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	4	0	0	0	0	3140	6	19	5	4	13379	40000	10	13383	13383	13458	13383	13383

AXFLAG

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations