Firestorm: XPACI measurements

Code:

  xpaci x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	18	104	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	1	0	73	2	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	63	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	1	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7069	870	1	1	1001	1000	0	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	71	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	75	0	55	4950	22	1001	1001	1000	52725	0	10	0	6029	6029	5670	3	5751	1000	0	0	6029	2203	1	1	1001	1000	0	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	76	0	525	4950	22	1001	1001	1000	52725	0	10	0	6029	6029	5670	3	5751	1000	0	0	6029	2413	1	1	1001	1000	0	0	132	0	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	76	0	55	4950	22	1001	1001	1000	52725	0	11	0	6029	6029	5670	3	5751	1000	0	0	6029	2203	1	1	1001	1000	0	0	132	1	26	0	0	5972	1001	1000	6030	6030	6030	6030	6030
1004	6029	75	0	55	4950	22	1001	1001	1000	52725	0	11	0	6029	6029	5700	3	5751	1000	0	0	6029	2203	1	1	1001	1000	0	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	12	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	1	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  xpaci x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	700	0	0	0	149	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	7	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70187
10204	70029	652	1	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	16	68674	10200	10200	10200	70029	912	2	1	10201	100	99	461	10100	0	5	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	12	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	58	0	0	0	0	710	1	79	2	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	6	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	613	0	0	0	117	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	2	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10202	100	99	0	10100	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	2	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	618	0	0	0	345	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	4	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	61	59819	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	0	0	0	1	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	0	10100	0	2	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70060	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	620	78	89	59824	25	10020	10020	10020	1807624	0	49	66949	70068	70108	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	1	9	2	0	640	2	79	3	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	45	61	59813	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69853	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	57	103	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	1	87	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	619	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70268	70186	70030	70030	70030
10024	70029	656	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	650	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	36	1485	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70058	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	7	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70057	611	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	1	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  xpaci x0
  xpaci x1
  xpaci x2
  xpaci x3
  xpaci x4
  xpaci x5
  xpaci x6
  xpaci x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	696	0	0	0	0	0	0	0	12	0	0	533	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5110	4	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5110	3	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	751	0	0	0	0	0	0	0	0	0	0	94	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5110	3	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5110	3	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5110	3	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	0	0	0	0	35	25	80200	80200	80222	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	2	0	0	0	0	0	5110	3	25	3	3	80025	80100	80100	80081	80036	80036	80036	80036
80204	80035	750	0	0	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5110	3	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	750	0	0	0	0	0	0	0	132	0	0	77	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	5122	3	25	3	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	0	0	0	77	25	80200	80200	80200	401000	1	49	76955	3	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80057	80100	80100	80036	80036	80036	80081	80036
80204	80035	695	0	0	0	0	0	0	0	0	0	0	35	25	80200	80200	80222	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80232	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80025	80100	80100	80036	80036	80082	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dc	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	80041	699	1	0	1	0	0	0	0	0	706	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80072	80035	164	1	1	80021	10	9	80010	0	3	0	0	5021	0	0	7	25	0	6	4	80028	80010	0	0	80010	80218	80036	80036	80036	80036
80024	80035	751	1	1	1	0	0	0	0	0	41	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	6	25	0	6	4	80028	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	0	1	0	0	0	0	0	41	25	80020	80020	80020	400100	0	49	74303	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	62	0	1	0	5021	0	0	6	25	0	6	4	80028	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	1	0	0	0	0	0	41	25	80020	80020	80020	400100	0	49	73910	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	6	25	0	8	4	80028	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	0	1	0	0	0	117	0	361	25	80020	80020	80020	400100	0	49	76955	80035	80035	70021	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	4	25	0	4	6	80027	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	695	1	0	1	0	0	0	0	0	64	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	5	25	0	6	10	80027	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	699	1	0	1	0	0	0	0	0	41	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	4	25	0	4	6	80027	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	751	1	0	1	0	0	0	0	0	41	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	6	0	0	5021	0	0	5	25	0	5	9	80028	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	0	1	0	0	0	0	0	155	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	4	25	0	4	6	80027	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	743	1	0	1	0	0	0	0	0	83	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	5021	0	0	6	25	0	6	4	80027	80010	0	0	80010	80036	80036	80036	80036	80036

XPACI

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations