Firestorm: STURH measurements

Code:

  sturh w0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	553	4	1	1	1	0	0	18	1	0	1	539	16	16	6	25	1000	1000	1000	23052	554	563	367	3	412	1000	1000	2000	552	554	1	1	1001	1000	1000	1015	15	44	0	0	1016	0	0	19	1002	16	44	14	0	73	1	16	1	1	549	1000	555	554	552	553	564
1004	564	4	1	1	0	1	0	17	1	0	1	539	16	16	5	25	1000	1000	1000	23438	554	552	367	3	421	1000	1000	2000	554	552	1	1	1001	1000	1000	1015	14	43	0	0	1016	0	0	17	1002	16	44	14	1	73	1	16	1	1	551	1000	564	555	555	555	555
1004	554	4	1	0	1	1	0	19	1	0	1	548	16	16	1	25	1000	1000	1000	22956	552	554	364	3	412	1000	1000	2000	551	554	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	0	18	1002	16	44	14	0	73	1	16	1	1	550	1000	555	554	552	553	564
1004	563	4	1	1	0	1	0	17	1	0	1	538	16	16	2	25	1000	1000	1000	23028	554	563	367	3	421	1000	1000	2000	554	551	1	1	1001	1000	1000	1015	16	44	0	1	1016	0	1	17	1002	16	44	14	1	73	1	16	1	1	551	1000	555	553	553	565	565
1004	554	4	1	1	0	1	0	22	1	0	1	539	16	15	0	25	1000	1000	1000	23004	551	554	366	3	412	1000	1000	2000	553	554	1	1	1001	1000	1000	1015	15	44	0	1	1016	0	1	17	1002	16	42	14	1	73	1	16	1	1	551	1000	555	555	555	554	553
1004	552	4	1	1	1	1	0	19	1	0	1	539	16	16	5	25	1000	1000	1000	23004	552	554	365	3	412	1000	1000	2000	552	554	1	1	1001	1000	1000	1014	15	44	0	2	1016	0	0	18	1002	16	44	14	1	73	1	16	1	1	551	1000	555	555	554	553	553
1004	552	4	1	1	1	0	0	18	1	0	1	539	16	16	6	25	1000	1000	1000	23438	554	552	367	3	409	1000	1000	2000	554	554	1	1	1001	1000	1000	1016	15	44	0	1	1016	0	0	17	1002	16	44	14	0	73	1	16	1	1	550	1000	565	555	555	555	555
1004	554	4	1	0	1	1	0	19	0	0	1	539	16	16	3	25	1000	1000	1000	23028	552	554	365	3	412	1000	1000	2000	552	554	1	1	1001	1000	1000	1014	14	44	0	0	1016	0	1	18	1002	16	44	14	1	73	1	16	1	1	551	1000	553	565	555	555	555
1004	554	4	1	1	1	1	0	17	1	0	1	539	16	16	2	25	1000	1000	1000	23004	554	552	367	3	410	1000	1000	2000	554	552	1	1	1001	1000	1000	1015	14	44	0	0	1016	0	2	16	1002	16	44	14	0	73	1	16	1	1	551	1000	553	564	556	555	555
1004	554	4	1	1	0	0	0	18	1	0	1	536	16	16	1	25	1000	1000	1000	23004	554	563	367	3	421	1000	1000	2000	554	552	1	1	1001	1000	1000	1014	14	43	0	2	1016	0	0	16	1002	16	44	14	1	73	1	16	1	1	550	1000	548	555	555	553	553

Count: 8

Code:

  sturh w0, [x6, #1]
  sturh w0, [x6, #1]
  sturh w0, [x6, #1]
  sturh w0, [x6, #1]
  sturh w0, [x6, #1]
  sturh w0, [x6, #1]
  sturh w0, [x6, #1]
  sturh w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	311	9	3	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	49	36962	40040	40042	29961	7	29994	80107	200	80016	200	160032	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	28	2	80002	0	5	80002	2	34	1	1	1	5118	0	16	0	0	40048	80000	100	40043	40043	40043	40043	40051
80204	40042	300	0	0	0	0	40025	16	0	0	25	80100	100	80000	100	80007	500	1839455	0	49	36970	40040	40040	29961	7	30001	80107	200	80016	200	160032	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	80000	1	5	80002	0	0	1	1	1	5118	0	16	0	0	40039	80000	100	40051	40041	40051	40043	40043
80204	40042	300	18	6	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	1	49	36970	40042	40040	29955	3	30007	80100	200	80000	200	160000	40042	32002	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	80002	0	8	80002	2	0	0	0	0	5110	1	16	1	1	40037	80000	100	40043	40041	40043	40050	40041
80204	40050	300	0	3	0	0	40034	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36969	40042	40042	29955	3	30008	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80002	0	2	80000	0	34	0	0	0	5110	1	16	1	1	40037	80000	100	40041	40043	40043	40043	40051
80204	40042	300	0	3	1	0	40027	0	16	0	40	80100	100	80000	100	80000	500	1839424	0	49	36962	40042	40042	29953	3	30008	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80002	0	0	80000	2	0	0	0	0	5110	1	16	1	1	40039	80000	100	40041	40043	40051	40041	40052
80204	40042	300	0	3	1	0	40025	16	0	0	25	80100	100	80000	100	80000	500	1839856	1	49	36969	40042	40050	29953	3	29998	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80002	0	2	80002	2	34	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40050	40041	40043	40043
80204	40050	300	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839856	1	49	36970	40042	40051	29964	3	29998	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80002	1	5	80000	0	34	0	0	0	5110	1	16	1	1	40037	80000	100	40041	40043	40043	40043	40043
80204	40050	300	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839352	1	49	36962	40042	40042	29955	3	30009	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80002	0	2	80002	2	34	0	0	0	5110	1	16	1	1	40047	80000	100	40043	40050	40043	40041	40043
80204	40050	300	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36960	40050	40040	29955	3	30000	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80000	0	8	80002	2	0	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40043	40043	40041	40043
80204	40042	300	6	0	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1842218	0	49	36971	40040	40051	29955	3	29998	80100	200	80000	200	160000	40040	32004	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	0	80000	0	8	80002	2	34	0	0	0	5110	1	16	1	1	40039	80000	100	40041	40043	40043	40050	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40061	300	1	1	1	1	0	20	1	0	0	1	40035	0	16	5	25	80010	10	80000	10	80000	50	1839956	1	49	36972	40047	40053	29987	3	30033	80010	20	80000	20	160000	40061	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	2	80016	0	1	21	80002	2	34	0	0	5021	1	16	0	5	1	1	40039	0	80000	10	40051	40041	40051	40043	40052
80024	40042	300	0	0	0	0	0	3	1	0	0	0	40035	0	0	0	25	80010	10	80000	10	80000	50	1839424	0	49	36960	40049	40049	29985	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80000	0	0	5	80002	0	34	0	0	5020	1	16	0	4	1	1	40039	0	80000	10	40051	40043	40041	40041	40041
80024	40040	300	0	0	0	0	6	6	1	0	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839856	1	49	36971	40042	40051	29977	3	30022	80010	20	80000	20	160000	40042	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80000	0	0	2	80000	2	34	0	0	5020	1	16	0	4	1	1	40040	0	80000	10	40043	40041	40043	40052	40043
80024	40049	300	0	0	0	0	0	0	0	0	0	0	40035	16	16	2	25	80010	10	80000	10	80000	50	1839352	0	49	36962	40042	40042	29975	3	30020	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	8	80002	0	34	0	0	5020	1	16	0	4	1	1	40039	0	80000	10	40043	40041	40043	40052	40043
80024	40042	300	0	0	0	0	0	0	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	5	80002	2	34	0	0	5020	1	16	0	4	1	1	40039	0	80000	10	40041	40043	40041	40043	40051
80024	40042	300	0	0	0	0	0	3	1	0	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	40040	40040	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	8	80002	2	34	0	0	5020	1	16	0	4	1	1	40037	0	80000	10	40043	40041	40043	40043	40041
80024	40050	300	0	0	0	0	0	3	1	0	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839808	1	49	36962	40051	40050	29985	3	30022	80010	20	80000	20	160000	40051	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	0	80002	2	34	0	0	5020	1	16	0	4	1	1	40037	0	80000	10	40043	40051	40043	40051	40041
80024	40049	299	0	0	0	0	0	0	1	0	0	0	40036	0	16	0	25	80010	10	80000	10	80000	50	1839352	0	49	36962	40040	40042	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80000	0	0	2	80000	2	34	0	0	5020	1	16	0	5	1	1	40039	0	80000	10	40041	40043	40043	40043	40041
80024	40042	300	0	0	0	0	0	0	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839760	0	49	36962	40040	40042	29975	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	80002	0	0	2	80002	2	34	0	0	5020	1	16	0	4	1	1	40039	0	80000	10	40041	40051	40043	40051	40043
80024	40049	300	0	0	0	0	0	6	1	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40042	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	1	0	0	80002	2	0	0	0	5020	1	16	0	4	1	1	40039	0	80000	10	40041	40052	40043	40041	40043

STURH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations