Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CBZ (not taken)

Test 1: uops

Code:

  cbz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0f5f6f7f8fd
10043842503525100010001000500005355351623180100010001000535535111001100007352133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332143532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536
1004535403525100010001000500015355351623180100010001000535535111001100007332133532536536536536536

Test 2: throughput

Count: 8

Code:

  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

retire uop (01)cycle (02)03l2 tlb miss data (0b)3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
8020440437300028288011080110801144005601349370104009040090133497133598011480224802244009032050118020180100991001001000001115118321622400871004009140091400914009140091
8020440090301028288011080110801144005601049370104009040090133497133598011480224802244009032050118020180100991001001000001115118311612400871004009140091400914009140091
8020440090300028288011080110801144005600349370104009040090133497133598011480224802244009032050118020180100991001001000001115118011632400871004009140091400914009140091
8020440090301028288011080110801144005601049370104009040090133497133598011480224802244009032050118020180100991001001000001115118011612400871004009140091400914009140091
8020440090300028288011080110801144005600349370104009040090133497133598011480224802244009032050118020180100991001001000001115118321622400871004009140091400914009140091
8020440090300028288011080110801144005601049370104009040090133497133598011480224802244009032050118020180100991001001000001115118321621400871004009140091400914009140091
8020440090300028288011080110801144005600349370104009040090133497133598011480224802244009032050118020180100991001001000031115118021622400871004009140091400914009140091
8020440090300028288011080110801144005600349370104009040090133497133598011480968802244009032050118020180100991001001000001115118321622400871004009140091400914009140091
8020440090300028288011080110801144005600349370104009040090133497133598011480224802244009032050118020180100991001001000001115118311622400871004009140091400914009140091
8020440090301028288011080110801144005601049370104009040090133497133598011480224802244009032050118020180100991001001000001115118321621400871004009140091400914009140091

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
800244277230710352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100020050201420181740037104004140041400414004140041
800244004030000352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100000050201720161240037104004140041400414004140041
800244004029900352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100313050201120161340037104004140041400954009540041
800244004030000352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100000050201820141140037104004140041400414004140041
8002440040300005102580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100000050201120111340037104004140041400414004140041
800244004030000352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100000050201320171440037104004140041400414004140041
800244004030000352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100000050201220181340037104004140041400414004140041
800244004030000352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100006050201720161740037104004140041400414004140041
80024400403000035258001080010800104000500493696040040400401333131334980010800208002040040400401180021800109101010000005022142091240037104004140041400414004140041
800244004030000352580010800108001040005004936960400404004013331313349800108002080020400404004011800218001091010100000050201620171840037104004140041400414004140041