Firestorm: SUB (uxtx, 64-bit) measurements

Code:

  sub x0, x0, x1, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	6	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	2	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	3	82	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  sub x0, x0, x1, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	3	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	12	61	9877	25	10100	10100	10100	88664	3	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	1	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	4	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	30	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	0	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	2	0	6	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	170	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	57	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	1	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	84	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	72	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	44	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	18	103	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  sub x0, x1, x0, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	9	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	9	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	1290	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	441	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	6	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	396	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	9	1895	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	103	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	1	0	0	640	3	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	33	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	57	640	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 4: throughput

Count: 8

Code:

  sub x0, x8, x9, uxtx
  sub x1, x8, x9, uxtx
  sub x2, x8, x9, uxtx
  sub x3, x8, x9, uxtx
  sub x4, x8, x9, uxtx
  sub x5, x8, x9, uxtx
  sub x6, x8, x9, uxtx
  sub x7, x8, x9, uxtx

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13417	101	0	0	0	0	0	33	0	35	25	80100	80100	80100	400500	1	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5111	0	0	4	19	2	3	13383	80000	80100	13387	13387	13387	13387	16279
80204	13386	100	0	0	0	0	0	45	0	35	25	80100	80100	80100	400500	1	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5111	0	0	3	19	3	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	0	0	227	25	80100	80100	80100	400500	1	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	0	0	3	19	3	3	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	1	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5111	0	0	3	19	3	4	13592	80408	80100	13578	13577	13454	13513	13578
80204	13452	102	0	0	0	0	3	555	176	403	89	80504	80379	80517	411313	1	0	49	10497	13532	13576	3323	3	3341	80100	80200	160474	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5111	0	0	1	19	3	3	13383	80000	80100	13387	13387	13387	13387	13387
80204	13453	100	0	0	0	0	1	267	264	441	122	80100	80370	80387	413483	1	0	49	10432	13580	13511	3323	3	3361	80385	80610	160980	13579	39	2	1	80201	100	99	100	80100	100	2	2	0	0	0	5111	0	0	3	19	3	3	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	0	1	0	372	0	79	25	80100	80100	80100	400500	1	0	49	10306	13386	13511	3328	18	3401	80100	80461	160978	13386	39	4	1	80201	100	99	100	80100	100	2	2	1	1370	0	5111	0	0	4	19	2	4	13500	80418	80100	13387	13577	13556	13387	13387
80204	13386	100	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	1	0	49	10433	13386	13386	3323	11	3402	80386	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	2	468	2	5169	0	0	3	74	4	2	13433	80000	80100	13593	13528	13576	13387	13387
80204	13575	100	1	1	1	1	4	690	88	225	25	80100	80100	80100	400500	1	0	49	10306	13386	13386	3323	25	3421	80100	80336	161258	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	455	0	5129	0	0	3	146	3	3	13484	80663	80100	13575	13759	13451	13762	13750
80204	13573	106	0	0	0	0	0	0	0	510	25	80100	80100	80100	400500	1	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5111	0	0	2	19	3	2	13383	80000	80100	13387	13387	13387	13387	13387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	13376	100	0	35	25	80010	80010	80010	400050	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	3	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	2	3	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	2	1	0	5020	4	19	0	3	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	3	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	3	2	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	3	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	27	56	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	0	3	2	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	77	25	80010	80010	80010	400050	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	3	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	77	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160292	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	2	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	102	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80142	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	19	0	3	2	13368	80000	80010	13372	13372	13372	13372	13372

SUB (uxtx, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations