Firestorm: LDRH (pre-index) measurements

Code:

  ldrh w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	8	0	0	1	1	72	19	1	4	0	1025	0	4	9	4	16	25	2000	1000	1000	1000	1000	52844	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1028	0	0	39	1028	1	0	10	10	26	1025	35	3	14	55	3	0	73	2	16	1	1	1020	1000	26	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	41	0	1	2	4	1025	11	5	9	11	14	25	2000	1000	1000	1000	1000	52844	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	0	0	63	1027	0	0	0	10	27	1035	24	3	18	31	0	0	73	1	16	1	1	1038	1000	26	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	43	16	1	4	0	1025	11	5	11	12	14	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1024	0	0	63	1035	1	0	10	20	20	1033	33	2	14	31	0	0	73	1	16	1	1	1037	1000	24	15	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	52	20	1	3	20	1025	11	4	2	10	53	25	2000	1000	1000	1000	1000	52840	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	47	1023	13	0	0	0	16	1016	28	2	22	63	0	0	73	1	16	1	1	1037	1000	26	21	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	47	0	0	4	0	1025	0	6	10	8	15	25	2000	1000	1000	1000	1000	52852	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1013	0	1	66	1040	6	0	0	0	16	1030	24	3	12	39	0	0	73	1	16	1	1	1037	1000	31	23	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	58	13	0	3	12	1025	17	5	10	8	22	25	2000	1000	1000	1000	1000	52832	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1053	44	1	1	1001	1000	1000	0	1016	0	1	43	1027	14	0	13	6	26	1026	39	3	17	39	0	0	73	1	16	1	1	1037	1000	26	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	51	14	1	4	0	1025	11	5	11	8	18	25	2000	1000	1000	1000	1000	52836	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1028	0	1	62	1038	15	1	15	10	21	1036	29	1	26	71	0	0	73	1	16	1	1	1038	1000	24	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	53	13	1	2	0	1025	9	7	13	8	14	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1013	0	1	66	1030	1	0	28	20	18	1024	23	2	18	71	0	0	73	1	16	1	1	1037	1000	21	24	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	41	16	1	2	0	1025	7	6	5	9	13	25	2000	1000	1000	1000	1000	52844	45823	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1011	0	1	50	1035	15	36	0	0	18	1021	38	1	18	55	0	0	73	1	16	1	1	1037	1000	26	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	1	0	0	45	13	1	4	0	1025	15	3	8	8	17	25	2000	1000	1000	1000	1000	52852	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1023	0	0	55	1024	12	0	0	0	17	1018	39	3	20	31	0	0	73	1	16	1	1	1037	1000	21	19	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1944

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72005	540	1	1	0	0	0	0	0	0	474	0	831	1	728	1	132	71925	783	4	2	71814	25	50750	40632	10132	40100	10000	615673	2734809	49	68912	71832	72108	65315	3	65702	50100	40200	10000	70200	10000	71995	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10903	1	149	519	10646	273	8	922	52	19	10889	123	3	128	0	0	3	0	2610	3	56	1	2	71777	40560	1109	1078	1153	10000	40100	71976	71867	71906	72087	71961
50204	72121	538	1	0	0	0	0	0	0	0	438	0	820	1	712	1	104	71902	798	3	2	71645	25	50855	40660	10125	40100	10000	615058	2728931	49	68934	72023	71847	65387	3	65657	50100	40200	10000	70200	10000	71872	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10928	1	155	512	10659	264	14	892	50	20	10941	139	4	130	1	1	3	0	2610	2	64	2	2	71792	40608	1195	1139	1136	10000	40100	71805	72154	71848	71958	71978
50204	71997	538	1	0	0	0	0	0	0	0	466	0	772	1	672	2	128	71935	815	4	3	71543	25	50790	40632	10133	40100	10000	615885	2723583	49	68870	71967	71862	65568	3	65575	50100	40200	10000	70200	10000	71981	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10921	2	152	518	10689	289	8	963	58	26	10962	130	5	134	1	0	4	0	2610	2	58	2	2	71774	40556	1112	975	1067	10000	40100	71993	71914	71975	72054	72020
50204	72141	539	1	0	0	0	1	0	0	0	477	0	802	1	696	1	100	72062	855	3	2	71962	25	50775	40672	10127	40100	10000	615786	2726012	49	68844	71855	72021	65268	3	65681	50100	40200	10000	70200	10000	71891	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10915	1	147	510	10632	255	8	925	80	29	10882	129	4	130	1	0	10	0	2610	2	58	2	2	71749	40532	1130	1120	1088	10000	40100	72109	71964	71799	72031	72267
50204	71912	539	1	1	0	0	0	0	0	0	411	0	844	1	664	1	148	71890	789	3	2	71657	25	50745	40636	10142	40100	10000	615193	2733410	49	68875	71862	71964	65476	3	65690	50100	40200	10000	70200	10000	72006	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10916	1	132	515	10659	262	9	916	76	22	10930	134	5	138	1	3	9	0	2610	2	63	2	2	71707	40564	1131	1140	1168	10000	40100	72077	72117	71851	71957	71990
50204	71888	538	1	0	0	0	0	1	0	0	440	0	824	1	720	2	124	71958	795	3	3	71703	25	50740	40652	10139	40100	10000	615148	2728289	49	68750	71845	72209	65295	3	65570	50100	40200	10000	70200	10000	71913	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10927	1	152	486	10641	265	14	939	82	31	10905	134	4	129	1	3	3	0	2610	2	51	2	2	72014	40572	1105	1055	1051	10000	40100	72167	71879	71959	72017	72041
50204	71924	538	1	0	0	0	1	0	0	0	456	0	831	1	712	1	100	71646	820	3	2	71656	25	50770	40616	10131	40100	10000	614725	2728530	49	68960	71735	71749	65515	3	65796	50100	40200	10000	70200	10000	72154	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10928	1	135	479	10650	276	12	919	90	19	10942	121	5	134	1	3	4	0	2610	2	56	2	2	71953	40536	1029	1042	1146	10000	40100	71943	71780	72072	71997	72127
50204	71981	539	1	0	0	0	0	0	0	0	419	0	812	1	720	2	108	71809	796	3	2	71744	25	50750	40656	10140	40100	10000	613281	2720665	49	68837	71897	71957	65394	3	65650	50100	40200	10000	70200	10000	72051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10923	1	146	497	10648	263	13	910	50	22	10915	137	4	134	1	3	5	0	2610	2	56	2	2	71791	40548	1130	1134	1098	10000	40100	72029	71985	71838	71991	71808
50204	71935	540	1	0	0	0	0	1	0	0	450	0	785	1	704	1	132	71865	806	3	2	71778	25	50785	40616	10131	40100	10000	613811	2724088	49	68912	71907	72072	65418	3	65658	50100	40200	10000	70200	10000	71916	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10921	1	133	613	10693	282	8	942	50	25	10949	132	3	134	1	0	3	0	2610	2	56	2	2	71848	40572	1080	1097	1077	10000	40100	72043	71827	72092	71977	72116
50204	71819	539	1	0	0	0	0	0	0	0	415	0	789	1	704	2	100	71744	797	3	3	71560	25	50770	40636	10120	40100	10000	614019	2728969	49	68757	71990	71855	65493	3	65565	50100	40200	10000	70200	10000	71949	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10930	1	140	492	10624	260	13	916	32	17	10915	130	4	121	1	0	4	0	2610	2	56	2	2	71962	40556	1149	1074	1070	10000	40100	72013	71934	71899	72073	72006

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1901

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72001	538	1	0	0	0	0	0	0	427	0	818	1	0	720	0	140	71871	827	71560	25	50675	40546	10136	40010	10000	613179	2726585	0	49	68980	71956	72004	65475	3	65723	50010	40020	10000	70020	10000	71828	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10894	0	157	473	10643	274	7	928	36	27	10914	122	0	142	0	3	9	2	2520	16	85	13	13	71870	40480	1082	1037	1114	10000	40010	72084	72078	72053	72116	71947
50024	71919	539	0	0	0	0	0	0	0	477	0	842	1	0	704	0	116	71944	795	71608	25	50640	40530	10120	40010	10000	611746	2721140	0	49	68714	71884	71753	65343	3	65498	50010	40020	10000	70020	10000	71860	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10900	0	154	502	10611	248	16	918	72	21	10899	137	0	127	0	3	3	0	2520	5	85	5	14	71688	40504	1051	1095	1001	10000	40010	72081	72300	71954	71928	72059
50024	71965	538	1	0	0	0	0	0	1	440	0	825	1	0	664	0	108	71881	792	71547	25	50650	40478	10132	40010	10048	613583	2725428	0	49	68785	71957	71941	65219	3	65585	50010	40020	10000	70020	10000	71762	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10912	0	131	486	10640	270	16	883	68	27	10931	115	0	122	0	0	4	0	2520	5	71	13	12	71658	40488	1144	944	1148	10000	40010	71970	72018	71924	71936	71808
50024	71901	539	0	0	0	0	0	0	0	463	0	817	1	0	720	0	100	71830	793	71715	25	50650	40534	10127	40010	10000	611754	2722690	1	49	68725	71843	71981	65303	3	65818	50010	40020	10000	70020	10000	71871	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10909	1	169	481	10645	266	9	888	74	27	10921	114	0	122	1	0	5	0	2520	10	85	13	5	71888	40540	1061	1030	1018	10000	40010	71855	71910	71827	71747	71878
50024	71937	540	1	0	0	0	0	0	0	492	0	813	1	0	720	1	128	71783	818	71559	25	50625	40486	10124	40010	10000	612593	2726458	0	49	68732	71931	71874	65345	3	65293	50010	40020	10000	70312	10000	72055	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10909	0	162	476	10621	237	13	897	50	21	10918	125	0	116	1	0	7	0	2520	4	85	4	14	71728	40540	1060	1056	1104	10000	40010	72000	71976	72015	72016	71974
50024	71956	539	0	0	0	0	0	0	0	431	0	835	1	0	736	0	124	71864	829	71511	25	50615	40522	10145	40010	10000	614051	2723411	0	49	68837	71870	71861	65443	3	65521	50010	40020	10000	70020	10000	71814	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10894	0	131	508	10630	273	10	883	100	27	10914	127	0	122	0	0	3	0	2520	14	85	14	4	71864	40500	1105	1110	1054	10000	40010	71974	72016	71796	71815	71841
50024	71841	538	0	0	0	0	0	0	0	416	0	817	1	0	768	0	128	71966	795	71485	25	50725	40550	10125	40010	10000	613537	2726294	0	49	68697	71945	72065	65283	3	65584	50010	40020	10000	70020	10000	71824	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10917	0	148	482	10621	282	11	870	48	12	10917	124	1	136	0	0	7	0	2520	14	85	14	4	71699	40504	1027	1090	1065	10000	40010	71873	71654	72179	71925	71899
50024	71910	539	0	0	0	0	0	0	0	428	0	805	1	0	696	0	128	71894	811	71566	25	50696	40498	10116	40010	10000	613526	2721327	0	49	68638	71948	71822	65272	3	65659	50010	40020	10000	70020	10000	71839	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10874	0	138	513	10605	255	16	907	76	28	10921	129	1	124	0	3	2	0	2520	13	71	13	4	71834	40516	1077	1097	1109	10000	40010	71880	72073	71956	71917	72129
50024	72004	537	0	0	0	0	0	0	0	455	0	830	1	0	720	0	128	71751	785	71649	25	50675	40538	10127	40010	10000	613015	2726048	0	49	68983	71770	71971	65368	3	65532	50010	40020	10000	70020	10000	71743	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10875	0	155	519	10648	265	12	882	48	31	10915	123	1	118	1	0	7	0	2520	14	71	13	5	71594	40520	1064	1049	1049	10000	40010	71945	71874	72041	71890	71800
50024	71880	537	0	0	0	0	0	0	0	495	0	816	1	0	728	0	96	71788	773	71574	25	50605	40478	10115	40010	10000	612115	2723257	1	49	68861	71914	71743	65404	3	65706	50010	40020	10000	70020	10000	71874	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10896	0	155	448	10627	285	13	918	48	21	10911	132	1	117	0	3	4	0	2520	12	71	3	13	71557	40492	1026	1136	1036	10000	40010	71936	71762	71835	71885	71996

Test 3: throughput

Count: 8

Code:

  ldrh w0, [x6, #8]!
  ldrh w0, [x7, #8]!
  ldrh w0, [x8, #8]!
  ldrh w0, [x9, #8]!
  ldrh w0, [x10, #8]!
  ldrh w0, [x11, #8]!
  ldrh w0, [x12, #8]!
  ldrh w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3658

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29719	219	1	0	1	1	0	0	6137	792	1	712	89	96	29286	784	293	1650	1746	1933	25	160160	80161	80000	80100	80000	400753	1291362	0	69	49	26230	29419	29249	9401	3	9140	160100	80200	80000	80200	80000	29250	35	1	1	80201	100	99	20	100	80000	100	80000	100	80967	19	389	4617	85297	658	13	893	24	4959	86462	686	130	5253	5007	19	0	0	5110	1	17	1	1	29436	35	80059	510	424	92	80000	80100	29412	29332	29383	29473	29328
160204	29160	218	1	0	0	0	0	0	6466	769	1	704	105	112	29212	776	312	1844	1430	1976	25	160151	80167	80000	80100	80000	400795	1282860	0	58	49	26399	29291	29332	9133	3	9225	160100	80200	80000	80200	80000	29498	35	1	1	80201	100	99	23	100	80000	100	80000	100	80902	19	408	5049	85498	627	11	937	26	4987	86362	772	138	5040	4778	19	3	10	5110	1	17	2	1	29513	27	80053	572	615	96	80000	80100	29137	29215	29528	29279	29479
160204	29278	220	1	0	0	0	0	0	6626	844	1	704	90	144	29034	770	306	2017	1612	1990	25	160151	80159	80000	80100	80000	400744	1279412	1	57	49	26215	29112	29305	9077	3	9191	160100	80200	80000	80200	80000	29313	35	1	1	80201	100	99	41	100	80000	100	80000	100	80885	19	416	5316	85525	623	13	868	34	4935	85608	763	115	4831	4941	19	3	3	5110	1	16	1	1	29665	23	80065	635	492	92	80000	80100	29233	29313	29428	29347	29302
160204	29120	220	1	0	0	0	0	0	6548	792	2	744	101	100	29341	807	284	1914	1839	2071	25	160157	80161	80000	80100	80000	400739	1298159	0	50	49	26282	29262	29174	9358	3	9232	160100	80200	80000	80200	80000	29293	35	1	1	80201	100	99	26	100	80000	100	80000	100	80896	20	350	4904	85309	627	11	876	44	4919	85741	726	108	4852	4778	19	0	4	5110	1	17	1	1	29707	30	80061	501	511	108	80000	80100	29390	29305	29252	29363	29376
160204	29256	220	1	0	0	0	0	0	6672	816	1	712	84	108	29121	751	322	1697	1821	1869	25	160155	80155	80000	80100	80000	400745	1293991	0	66	49	26277	29232	29267	9107	3	9273	160100	80200	80000	80200	80000	29129	35	1	1	80201	100	99	21	100	80000	100	80000	100	80887	20	327	5041	84791	679	13	934	48	4935	86255	670	120	4976	5188	18	0	4	5110	1	16	1	1	29749	31	80064	593	481	93	80000	80100	29412	29130	29513	29439	29308
160204	29317	218	1	0	0	0	0	0	6653	756	1	656	98	128	29323	747	291	1676	1727	1899	25	160165	80151	80000	80100	80000	400719	1299178	1	53	49	26223	29394	29336	9098	3	9288	160100	80200	80000	80200	80000	29237	35	1	1	80201	100	99	22	100	80000	100	80000	100	80853	21	345	5452	85397	637	11	845	46	4691	85031	757	129	4746	4684	19	6	177	5110	1	16	1	1	29726	24	80063	530	445	100	80000	80100	29225	29272	29313	29431	29289
160204	29257	219	1	0	0	1	0	0	6953	800	1	656	107	100	29260	747	310	1702	1767	2132	25	160171	80161	80000	80100	80000	400768	1290091	0	68	49	26411	29408	29377	9232	3	9299	160100	80200	80000	80200	80000	29438	35	1	1	80201	100	99	27	100	80000	100	80000	100	80888	20	406	5397	84943	635	11	914	36	4820	85839	665	121	4597	5406	19	0	3	5110	1	16	1	1	29325	19	80040	438	423	104	80000	80100	29361	29435	29473	29438	29381
160204	29387	220	1	0	1	0	0	0	6887	786	1	688	108	100	29320	765	326	1886	1732	1999	25	160158	80149	80000	80100	80000	400789	1299790	0	73	49	25853	29105	29138	9098	3	9460	160100	80200	80000	80200	80000	29290	35	1	1	80201	100	99	27	100	80000	100	80000	100	80905	19	389	5842	85317	621	12	864	32	4878	86096	664	103	4483	4745	19	2	3	5110	1	16	1	1	29481	26	80058	564	496	104	80000	80100	29147	29578	29365	29215	29318
160204	29055	220	1	0	0	1	0	0	6836	803	1	712	100	92	29303	744	287	1925	1959	1994	25	160149	80152	80000	80100	80000	400788	1299019	0	60	49	26152	29179	29182	9218	3	9194	160100	80200	80000	80200	80000	29370	35	1	1	80201	100	99	19	100	80000	100	80000	100	80901	19	328	5335	84781	648	11	893	20	4755	85929	682	116	4780	4561	19	0	11	5110	1	16	1	1	29589	28	80049	500	502	96	80000	80100	29123	29229	29330	29194	29200
160204	29157	220	1	0	0	0	0	0	6423	828	1	672	93	128	29220	796	304	1983	1696	1996	25	160143	80164	80000	80100	80000	400824	1294447	0	54	49	26111	29547	29588	9326	23	9390	160100	80200	80000	80200	80000	29045	35	1	1	80201	100	99	22	100	80000	100	80000	100	80882	20	393	5721	85092	611	10	854	38	4862	85866	726	117	4707	5145	19	3	7	5110	1	16	1	1	29452	29	80058	494	515	95	80000	80100	29318	29256	29515	29202	29337

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3667

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29777	222	2	0	0	0	0	6391	0	754	1	704	124	100	29145	787	364	2084	2038	1898	25	160070	80073	80000	80010	80000	400341	1291664	0	74	49	26359	29181	29127	9385	0	3	9520	160010	80020	80000	80020	80000	29414	35	1	1	80021	10	9	43	10	80000	10	80000	0	10	80872	51	381	6046	85273	600	14	840	34	5278	86145	792	115	5275	4888	51	6	3	0	5020	4	16	3	3	29161	30	80062	582	479	86	80000	80010	29334	29387	29395	29624	29229
160024	29398	221	2	0	0	0	0	6487	0	785	1	680	112	100	29406	790	325	1828	1928	2068	25	160078	80071	80000	80010	80000	400349	1291739	0	61	49	26247	29469	29478	9076	0	3	9159	160010	80020	80000	80020	80000	29179	35	1	1	80021	10	9	25	10	80000	10	80000	0	10	80938	49	384	5417	85153	649	12	897	46	5137	86127	746	130	5426	5026	50	0	6	0	5020	2	16	2	3	29150	33	80073	596	557	107	80000	80010	29469	29405	29250	29393	29380
160024	29269	221	3	1	0	0	0	6676	0	771	1	752	105	100	29220	773	322	1612	2032	2047	25	160081	80065	80000	80010	80000	400334	1300567	1	73	49	26121	29429	29358	9237	0	3	9468	160010	80020	80000	80020	80000	29313	35	1	1	80021	10	9	24	10	80000	10	80000	1	10	81010	69	413	5692	84909	637	13	867	104	4365	86041	752	143	5203	5728	74	10	3	0	5020	4	15	3	3	29415	37	80062	512	451	107	80000	80010	29557	29142	29144	29217	29336
160024	29334	221	4	0	1	1	0	7113	0	774	1	672	119	108	29299	788	318	1906	1822	2205	57	160080	80077	80000	80010	80000	400282	1298652	0	53	49	26200	29310	29412	9259	0	3	9311	160010	80020	80000	80020	80000	29432	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80973	67	351	5980	85388	697	13	858	40	5228	86743	763	131	5459	5515	66	4	5	0	5020	2	15	3	2	29359	29	80054	578	596	118	80000	80010	29473	29398	29615	29334	29277
160024	29184	222	4	0	0	4	0	7196	0	820	1	720	104	148	29189	779	355	1828	1923	1971	25	160078	80075	80000	80010	80000	400286	1301129	1	61	49	26324	29165	29368	9412	0	3	9251	160010	80020	80000	80020	80000	29150	35	1	1	80021	10	9	29	10	80000	10	80000	0	10	80936	70	428	5749	85807	630	15	866	50	4683	86020	685	113	5185	4901	66	3	4	0	5020	2	16	2	3	29378	18	80078	527	463	89	80000	80010	29330	29479	29269	29285	29508
160024	29538	218	4	0	0	1	0	7430	0	781	1	680	107	132	29383	793	306	1873	2009	2001	25	160078	80079	80000	80010	80000	400333	1310596	0	66	49	26305	29356	29089	9331	0	3	9354	160010	80020	80000	80020	80000	29455	35	1	1	80021	10	9	34	10	80000	10	80000	0	10	80952	73	358	5141	85574	590	12	885	72	5384	85829	835	142	5380	5598	64	6	6	0	5020	3	16	4	3	29517	21	80066	581	568	114	80000	80010	29299	29268	29325	29431	29362
160024	29358	222	4	0	0	0	0	7336	0	768	1	704	97	120	29282	778	332	1982	1971	2176	25	160083	80076	80000	80010	80000	400360	1296875	1	77	49	26314	29478	29357	9513	0	3	9460	160010	80020	80000	80020	80000	29193	35	1	1	80021	10	9	33	10	80000	10	80000	0	10	80957	70	353	5938	85261	673	10	874	72	5330	85906	724	130	5197	5336	73	0	6	0	5020	3	15	3	3	29455	19	80066	527	508	106	80000	80010	29224	29344	29568	29420	29207
160024	29141	220	4	0	1	0	0	6926	0	732	1	712	112	104	29363	782	287	2000	1918	1995	25	160069	80088	80000	80010	80000	400303	1299504	1	51	49	26048	29284	29377	9080	0	3	9528	160010	80020	80000	80020	80000	29247	35	1	1	80021	10	9	22	10	80000	10	80000	0	10	80977	72	351	5243	85990	683	14	870	42	5364	86304	702	133	5554	5014	72	0	1	0	5020	3	16	3	3	29426	26	80062	530	543	115	80000	80010	29313	29427	29366	29238	29237
160024	29250	220	4	0	0	0	0	7064	0	787	1	712	116	136	29503	772	331	1918	1897	1913	25	160080	80082	80000	80010	80000	400314	1298663	0	70	49	26158	29311	29401	9306	0	3	9377	160010	80020	80000	80020	80000	29303	35	1	1	80021	10	9	46	10	80000	10	80000	0	10	80912	51	377	5199	85055	648	14	912	52	5585	86337	674	129	5496	5009	50	1	6	0	5020	3	16	3	3	29442	35	80058	510	502	96	80000	80010	29326	29363	29449	29459	29249
160024	29334	218	3	0	0	0	0	6653	0	787	1	672	104	132	29440	752	337	1772	2038	2231	25	160072	80065	80000	80010	80000	400371	1296111	1	76	49	26124	29225	29314	9252	0	3	9302	160010	80020	80000	80020	80000	29206	35	1	1	80021	10	9	26	10	80000	10	80000	0	10	80913	55	366	5211	85302	663	17	854	36	5281	85752	776	130	4938	4837	50	6	0	1	5020	3	16	3	2	29654	26	80070	565	530	105	80000	80010	29459	29133	29148	29337	29380

LDRH (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations