Firestorm: SDIV (slow, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0x7fffffffffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2040	16	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	16	0	18	61	950	25	1000	1000	1000	53725	0	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	16	0	0	61	950	25	1000	1000	1000	53725	0	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	16	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	1	12	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	0	61	950	25	1000	1000	1000	53725	1	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041
1004	2040	15	0	0	61	950	25	1000	1000	1000	53725	0	2040	2040	1801	3	1898	1000	1000	2000	2040	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2041	2041	2041	2041	2041

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0x7fffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	110035	824	0	0	0	0	0	0	980	100940	25	30100	30100	30100	10432628	1	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	2	16	1	1	109666	30000	30100	110036	110121	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	1	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	2	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	3	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	825	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1930	1	16	2	1	109758	30000	30100	110036	110036	110036	110127	110036
30204	110035	825	1	23	24	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	61	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	0	964	100940	25	30100	30100	30100	10432628	0	49	106955	110035	110035	105815	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	110035	824	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	4	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	3	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	825	0	2166	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	3	1890	3	16	4	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	4	16	3	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	103	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	50	0	0	0	1890	3	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	825	0	279	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	4	1890	3	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	2	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	726	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	3	106265	30010	30020	60020	110064	210	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0x7fffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	110216	824	0	0	0	60	352	103	100940	25	30100	30100	30100	10432628	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	2	0	0	0	1910	4	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30205	110035	824	0	0	0	0	0	726	100940	25	30100	30142	30100	10432628	49	106955	110035	110035	105815	0	7	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	2	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110215	110036	110036
30204	110212	824	0	0	0	0	0	61	100940	25	30100	30100	30303	10432628	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	4	0	2	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	726	100940	25	30100	30100	30100	10432628	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	2	1	30201	100	99	100	30100	100	0	0	2	9701	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	39	352	61	100940	25	30100	30100	30100	10432628	49	107133	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	2	0	0	0	1910	1	16	1	1	109666	30046	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	726	100940	25	30100	30100	30100	10440651	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	0	9	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	0	0	103	100940	25	30100	30144	30100	10432628	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	1	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036
30204	110035	824	0	0	0	12	0	536	100940	25	30100	30100	30100	10432628	49	106955	110035	110035	105815	0	19	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	2	31	12	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110217	110036	110036
30204	110035	824	0	1	0	0	0	61	100940	25	30100	30100	30516	10432628	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	1	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110216	110036	110036
30204	110035	824	0	0	0	0	0	726	100940	25	30100	30100	30100	10432628	49	106955	110035	110035	105815	0	3	106243	30100	30200	60200	110035	210	1	1	30201	100	99	100	30100	100	0	0	2	0	0	0	1910	1	16	1	1	109666	30000	30100	110036	110036	110036	110036	110036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 9.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	110035	825	0	0	61	101155	25	30010	30010	30010	10434631	0	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	4	109677	30002	30010	110036	110036	110036	110067	110036
30024	110035	824	0	0	61	101155	25	30010	30010	30010	10434631	0	49	106955	110035	110035	105848	0	3	106265	30012	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	232	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	5	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	61	101155	25	30010	30010	30202	10434631	1	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	825	0	0	61	101155	25	30010	30010	30010	10434631	1	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	825	0	0	61	101155	25	30010	30010	30010	10434631	0	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	232	1	1	30021	10	9	10	30010	10	61	0	0	0	1890	2	16	2	2	109679	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	61	101343	25	30010	30010	30010	10434631	0	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	232	1	1	30021	10	9	10	30010	10	2	0	0	0	1890	2	16	2	5	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	61	101155	25	30010	30010	30010	10434883	0	49	106955	110035	110035	105848	0	3	106265	30010	30020	60020	110035	232	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	4	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	251	101155	25	30010	30010	30115	10434631	1	49	106955	110035	110064	105848	0	3	106265	30010	30020	60020	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	3	109677	30000	30010	110036	110036	110036	110036	110036
30024	110035	824	0	0	61	101155	25	30010	30010	30010	10434631	0	49	106955	110035	110035	105848	0	3	106265	30010	30020	60284	110035	210	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	109677	30000	30010	110036	110036	110036	110036	110036

Test 4: throughput

Count: 8

Code:

  sdiv x0, x8, x9
  sdiv x1, x8, x9
  sdiv x2, x8, x9
  sdiv x3, x8, x9
  sdiv x4, x8, x9
  sdiv x5, x8, x9
  sdiv x6, x8, x9
  sdiv x7, x8, x9

Initialization

  mov x8, #0x7fffffffffffffff
  mov x9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160040	1199	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	3	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	0	726	79950	25	80100	80100	80100	4399225	0	49	156960	0	160082	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	0	61	79950	25	80100	80100	80100	4399225	1	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5131	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	1	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149941	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1198	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	1	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041
80204	160040	1199	0	61	79950	25	80100	80100	80100	4399225	0	49	156960	0	160040	160040	149901	3	149998	80100	80200	160200	160040	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160041	160041	160041	160041	160041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160040	1198	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160140	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	1	20	16	14	17	159980	80000	80010	160041	160083	160041	160041	160041
80024	160040	1199	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	0	0	1	18	16	16	14	159980	80000	80010	160041	160041	160041	160041	160079
80024	160040	1198	1	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	0	0	1	23	16	9	17	159980	80000	80010	160041	160041	160141	160092	160041
80024	160040	1199	1	0	774	747	79928	25	80010	80025	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	8	0	1	17	16	10	17	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	1	0	0	449	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	1	0	0	0	0	5021	6	0	1	11	16	17	13	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	1	0	0	1677	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	1	0	0	5021	6	1	1	17	16	17	17	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1198	1	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	6	0	1	9	16	17	14	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	1	0	0	726	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	6	0	1	14	16	17	9	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	1	0	0	82	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80010	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	6	0	1	17	16	9	17	159980	80000	80010	160041	160041	160041	160041	160041
80024	160040	1199	1	0	0	726	79950	25	80010	80010	80010	4398775	1	49	156960	0	160040	160040	149923	3	150020	80049	80020	160020	160040	261	1	1	80021	10	9	10	80010	10	3	6	0	0	0	5021	6	0	1	17	16	17	17	159980	80000	80010	160041	160041	160041	160041	160041

SDIV (slow, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations