Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (register, uxtw, 64-bit)

Test 1: uops

Code:

  str x0, [x6, w7, uxtw]
  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f22233f46494f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int store (96)inst ldst (9b)l1d tlb access (a0)l1d cache miss st (a2)a4st unit uop (a7)l1d cache writeback (a8)acafbcl1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
10055424031052716161251000100010002244854254235534011000100030005425431110011000100010004201002021002242073216115391000543543543543543
10045424030052716160251000100010002244854254235634001000100030005435431110011000100010004201002021002242073116115391000543543543543543
10045434030052716160251000100010002244854254235634011000100030005435431110011000100010004201002021002242073116115391000543543555543543
10045424031052716161251000100010002302454354335534001000100030005425421110011000100010004201002021002242073116115401000543543543555543
100454241531052716160251000100010002244854254235534001000100030005425421110011000100010004201002021002242073116115391000543543543543543
10045544031052716160251000100010002244854254235634001000100030005435431110011000100010004201002021002242073116115401000543544544544544
10045434031052716161251000100010002247254354335634001000100030005545421110011000100010004201002021002242073116115391000543543543543543
10045424030052716160251000100010002244854254335634001000100030005435421110011000100010004201002021002242073116115401000544544544544544
10045434030052716161251000100010002244854254235534121000100030005425541110011000100010004201002021002242073116115391000543543543543543
10045424031052716161251000100010002244854254235534001000100030005425421110011000100010004201002021002242073116115391000544544543543543

Test 2: throughput

Count: 8

Code:

  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk data (08)1e1f22233f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d cache miss st (a2)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8020540043300003104002716160258010010080000100800065001839503149369604004240043299597299948010620080016200240048400423199511802011009910080000100800001008000042800020028000204211151180160040039800001004004140041400434004440041
8020440042300000004002816161258010010080000100800065001839474049369634004340043299617299928010620080016200240048400423199511802011009910080000100800001008000042800020058000024211151180160040040800001004004440041400414004140041
802044004229900010400271616025801001008000010080006500184003104936962400424004229959729994801062008001620024004840042319951180201100991008000010080000100800004280002002800022011151180160040037800001004004140043400554004140043
8020440042300003104002500025801001008000010080006500183947404936963400404004029962729992801072008001620024004840042319951180201100991008000010080000100800004280002002800020011151180160040037800001004004140043400414004340044
80204400433000030040027160125801001008000010080006500183950304936963400434004329961729995801062008001620024004840040319951180201100991008000010080000100800000800000058000224211151180160040040800001004004440043400434004140043
8020440042300003004003916161258010010080000100800065001839378049369604004240042299617299948010620080016200240048400423199511802011009910080000100800001008000042800020028000204211151180160140040800001004004440044400434004340044
802044004029900000400251600258010010080000100800065001839378049369634004340043299597299928010620080016200240048400423199511802011009910080000100800001008000042800000068000224211151181160040037800001004004340044400444004340041
8020440042300003104002516161258010010080000100800065001839503049369604004340043299617299948010720080016200240048400423199511802011009910080000100800001008000042800000028000204211151180160040039800001004004140043400414004340043
80204400423000000040025160125801001008000010080006500183950304936960400434004029961729994801062008001620024004840042319931180201100991008000010080000100800000800000008000224211151180160040039800001004004440043400434004440043
802044004330006300400251616025801001008000010080006500183950304936963400434004329959729995801062008001620024004840042319951180201100991008000010080000100800000800020008000024211151180160040039800001004005540043400414004340041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f22233a3f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaacafbcl1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8002540042300000000310040039161612580010108000010800005018394480149369620400424004229975330023800102080000202400004004340043118002110910800001080000108000004200800020000800022000050202016126400370080000104004440043405954004440457
800244004029900000031004002716160258001010800001080000501839448014936960040042400422997733003480010208000020240000400424004211800211091080000108000010800000420080002000280000242000502010161210400390080000104004140043400434004140043
8002440043300000000310040025160125800101080000108000050183947201493696304004240043299773300238001020800002024000040040400421180021109108000010800001080000042008000000028000224201050201216712400390080000104004340043400414004340041
800244004229900000210100400271616025800101080000108000050183935200493696204004240042299773300228001020800002024000040042400401180021109108000010800001080000042008000200058000224200050201216158400400080000104004440044400434004340041
8002440042300000000310040027160025800101080000108010850183959201493696004004240040299773300228001020800002024000040042400401180021109108000010800001080000042008000200028000024220051131016108400390080000104004340043400414005540043
8002440042300000000310141407161665829580490108054012809725018827320149379300412854132430802120311788109020812102024363041293414299180021109108000010800001080600442295080482001877380422042000521721105616404390080000104156541286414294152141567
80024405953100101011133288310040025016025800101080000108108050189187911493834804185441422312578131474815222081452202445004074041840141800211091080000108000010808402423830807821209620807822420005266201281312415760080000104198441991415694142241835
800244188731461271393911471004201216161027385808501080840108140450190200101493936804254041423316212243198881200228145224246165415614267618180021109108000010800001080964242357381082000280002200005020103258400390080000104004140043400434004340043
80024400423000000003100400271616025800101080000108000050183952000493696204004240124299773300228001020800002024000040043400421180021109108000010800001080000042008000200028000224200050391016127400390080000104004340043400414004340043
80024400422990000003100400281616125800101080000108000050183959210493696204004040042299773300228001020800002024000040042400421180021109108000010800001080000042008000000028000000000502012161313400390080000104004340043400434004340041