Firestorm: STR (register, uxtw, 64-bit) measurements

Code:

  str x0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	22448	542	542	355	3	401	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	2	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	542	542	356	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	543	4	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	542	542	356	3	401	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	555	543	543
1004	542	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	23024	543	543	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	540	1000	543	543	543	555	543
1004	542	4	15	3	1	0	527	16	16	0	25	1000	1000	1000	22448	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	554	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22448	542	542	356	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	540	1000	543	544	544	544	544
1004	543	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	22472	543	543	356	3	400	1000	1000	3000	554	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	542	543	356	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	540	1000	544	544	544	544	544
1004	543	4	0	3	0	0	527	16	16	1	25	1000	1000	1000	22448	542	542	355	3	412	1000	1000	3000	542	554	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	22448	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	0	73	1	16	1	1	539	1000	544	544	543	543	543

Count: 8

Code:

  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]
  str x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40043	300	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839503	1	49	36960	40042	40043	29959	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	0	2	80002	0	42	1	1	1	5118	0	16	0	0	40039	80000	100	40041	40041	40043	40044	40041
80204	40042	300	0	0	0	0	0	40028	16	16	1	25	80100	100	80000	100	80006	500	1839474	0	49	36963	40043	40043	29961	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	0	5	80000	2	42	1	1	1	5118	0	16	0	0	40040	80000	100	40044	40041	40041	40041	40041
80204	40042	299	0	0	0	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1840031	0	49	36962	40042	40042	29959	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	0	2	80002	2	0	1	1	1	5118	0	16	0	0	40037	80000	100	40041	40043	40055	40041	40043
80204	40042	300	0	0	3	1	0	40025	0	0	0	25	80100	100	80000	100	80006	500	1839474	0	49	36963	40040	40040	29962	7	29992	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	0	2	80002	0	0	1	1	1	5118	0	16	0	0	40037	80000	100	40041	40043	40041	40043	40044
80204	40043	300	0	0	3	0	0	40027	16	0	1	25	80100	100	80000	100	80006	500	1839503	0	49	36963	40043	40043	29961	7	29995	80106	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80000	0	0	5	80002	2	42	1	1	1	5118	0	16	0	0	40040	80000	100	40044	40043	40043	40041	40043
80204	40042	300	0	0	3	0	0	40039	16	16	1	25	80100	100	80000	100	80006	500	1839378	0	49	36960	40042	40042	29961	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	0	2	80002	0	42	1	1	1	5118	0	16	0	1	40040	80000	100	40044	40044	40043	40043	40044
80204	40040	299	0	0	0	0	0	40025	16	0	0	25	80100	100	80000	100	80006	500	1839378	0	49	36963	40043	40043	29959	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80000	0	0	6	80002	2	42	1	1	1	5118	1	16	0	0	40037	80000	100	40043	40044	40044	40043	40041
80204	40042	300	0	0	3	1	0	40025	16	16	1	25	80100	100	80000	100	80006	500	1839503	0	49	36960	40043	40043	29961	7	29994	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80000	0	0	2	80002	0	42	1	1	1	5118	0	16	0	0	40039	80000	100	40041	40043	40041	40043	40043
80204	40042	300	0	0	0	0	0	40025	16	0	1	25	80100	100	80000	100	80006	500	1839503	0	49	36960	40043	40040	29961	7	29994	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80000	0	0	0	80002	2	42	1	1	1	5118	0	16	0	0	40039	80000	100	40044	40043	40043	40044	40043
80204	40043	300	0	6	3	0	0	40025	16	16	0	25	80100	100	80000	100	80006	500	1839503	0	49	36963	40043	40043	29959	7	29995	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	0	0	80000	2	42	1	1	1	5118	0	16	0	0	40039	80000	100	40055	40043	40041	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	3	1	0	0	40039	16	16	1	25	80010	10	80000	10	80000	50	1839448	0	1	49	36962	0	40042	40042	29975	3	30023	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	0	80002	2	0	0	0	0	5020	20	16	12	6	40037	0	0	80000	10	40044	40043	40595	40044	40457
80024	40040	299	0	0	0	0	0	0	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	1	49	36960	0	40042	40042	29977	3	30034	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	2	80000	2	42	0	0	0	5020	10	16	12	10	40039	0	0	80000	10	40041	40043	40043	40041	40043
80024	40043	300	0	0	0	0	0	0	3	1	0	0	40025	16	0	1	25	80010	10	80000	10	80000	50	1839472	0	1	49	36963	0	40042	40043	29977	3	30023	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	0	2	80002	2	42	0	1	0	5020	12	16	7	12	40039	0	0	80000	10	40043	40043	40041	40043	40041
80024	40042	299	0	0	0	0	0	21	0	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36962	0	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	5	80002	2	42	0	0	0	5020	12	16	15	8	40040	0	0	80000	10	40044	40044	40043	40043	40041
80024	40042	300	0	0	0	0	0	0	3	1	0	0	40027	16	0	0	25	80010	10	80000	10	80108	50	1839592	0	1	49	36960	0	40042	40040	29977	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	2	80000	2	42	2	0	0	5113	10	16	10	8	40039	0	0	80000	10	40043	40043	40041	40055	40043
80024	40042	300	0	0	0	0	0	0	3	1	0	1	41407	16	16	658	295	80490	10	80540	12	80972	50	1882732	0	1	49	37930	0	41285	41324	30802	120	31178	81090	20	81210	20	243630	41293	41429	9	1	80021	10	9	10	80000	10	80000	10	80600	4	42	295	0	80482	0	0	1	8773	80422	0	42	0	0	0	5217	21	105	6	16	40439	0	0	80000	10	41565	41286	41429	41521	41567
80024	40595	310	0	1	0	10	11	1332	883	1	0	0	40025	0	16	0	25	80010	10	80000	10	81080	50	1891879	1	1	49	38348	0	41854	41422	31257	81	31474	81522	20	81452	20	244500	40740	41840	14	1	80021	10	9	10	80000	10	80000	10	80840	2	42	383	0	80782	1	2	0	9620	80782	2	42	0	0	0	5266	20	128	13	12	41576	0	0	80000	10	41984	41991	41569	41422	41835
80024	41887	314	6	1	2	7	13	939	1147	1	0	0	42012	16	16	1027	385	80850	10	80840	10	81404	50	1902001	0	1	49	39368	0	42540	41423	31621	224	31988	81200	22	81452	24	246165	41561	42676	18	1	80021	10	9	10	80000	10	80000	10	80964	2	42	357	3	81082	0	0	0	2	80002	2	0	0	0	0	5020	10	32	5	8	40039	0	0	80000	10	40041	40043	40043	40043	40043
80024	40042	300	0	0	0	0	0	0	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839520	0	0	49	36962	0	40042	40124	29977	3	30022	80010	20	80000	20	240000	40043	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	2	80002	2	42	0	0	0	5039	10	16	12	7	40039	0	0	80000	10	40043	40043	40041	40043	40043
80024	40042	299	0	0	0	0	0	0	3	1	0	0	40028	16	16	1	25	80010	10	80000	10	80000	50	1839592	1	0	49	36962	0	40040	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	0	2	80000	0	0	0	0	0	5020	12	16	13	13	40039	0	0	80000	10	40043	40043	40043	40043	40041

STR (register, uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations