Firestorm: MOV (bitmask immediate, 32-bit) measurements

Code:

  mov w0, #0xaaaaaaaa
  nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 3 nops): 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	60	6d	6e	map rewind (75)	map stall (76)	map int uop (7c)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	e0	? int retires (ef)	f5	f6	f7	f8	fd
4004	528	4	0	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	2	16	525	1000	529	529	529	529	529
4004	528	4	0	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	1	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	0	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	12	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	0	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	0	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	12	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	15	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	0	28	525	1	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529
4004	528	4	0	28	525	0	528	528	3	10	1000	528	95	1	1	4001	1000	0	0	260	0	16	525	1000	529	529	529	529	529

Count: 8

Code:

  mov w0, #0xaaaaaaaa
  mov w1, #0xaaaaaaaa
  mov w2, #0xaaaaaaaa
  mov w3, #0xaaaaaaaa
  mov w4, #0xaaaaaaaa
  mov w5, #0xaaaaaaaa
  mov w6, #0xaaaaaaaa
  mov w7, #0xaaaaaaaa

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1258

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	10091	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	3	0	5115	5	16	5	5	10057	59950	80100	11070	10061	10061	10061	10061
80204	10060	80	0	0	0	0	0	9	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	0	5115	3	16	3	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	0	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	0	5115	5	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	0	5115	5	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	77	0	0	0	0	0	0	0	63	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	0	5113	3	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	1	0	0	0	5113	3	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	3	0	5113	3	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	1	5115	5	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	12	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	4	0	0	0	5115	5	16	5	5	10057	59950	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	35	25	60050	60050	60050	300250	1	49	6980	10060	10060	3	18	60050	80200	200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	0	5115	5	16	5	3	10057	59950	80100	10061	10061	10061	10061	10061

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1255

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	10053	80	0	0	12	875	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	0	3	5025	6	16	3	6	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	1	0	5023	3	16	3	6	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	0	0	5025	3	16	5	3	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	78	2	0	12	35	25	60004	60004	60004	300020	1	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	25	3	5026	5	16	5	3	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	77	0	0	0	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	3	54	5025	3	16	4	6	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	81	0	0	12	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	0	0	5025	5	16	6	4	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	0	3	5025	6	16	5	3	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	0	0	5025	4	16	4	6	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	78	0	1	3	510	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	1	0	5023	5	16	5	5	10035	59994	80010	10039	10039	10039	10039	10039
80024	10038	77	0	0	0	35	25	60004	60004	60004	300020	0	49	6958	10038	10038	3	18	60004	80020	20	10038	35	1	1	80021	10	9	10	80010	10	0	0	5026	3	16	3	5	10035	59994	80010	10039	10039	10039	10039	10039

MOV (bitmask immediate, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations