Firestorm: LDRSW measurements

Code:

  ldrsw x0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	220	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	398	395	395
1004	394	3	0	0	0	45	0	0	1	382	2	12	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	45	0	0	1	379	2	1	12	19	25	1000	1000	1000	14989	0	394	398	216	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1038	6	1	39	44	73	1	16	1	1	395	10	10	4	1000	395	399	395	395	395
1004	398	3	0	0	0	45	0	0	1	379	2	12	12	0	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	38	1039	6	1	38	44	73	1	16	1	1	391	10	14	7	1000	399	396	395	399	399
1004	394	3	0	0	0	44	0	0	1	383	2	1	1	16	25	1000	1000	1000	14989	0	398	394	221	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	39	44	73	1	16	1	1	393	14	10	7	1000	399	395	395	396	395
1004	394	2	0	0	0	44	0	0	1	379	2	12	1	16	25	1000	1000	1000	15267	0	394	394	216	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	38	44	73	1	16	1	1	395	10	10	7	1000	399	395	399	395	395
1004	394	3	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	38	1039	6	1	38	43	73	1	16	1	1	391	10	10	4	1000	399	400	399	395	396
1004	398	3	0	0	0	45	0	0	1	379	2	1	12	16	25	1000	1000	1000	15018	0	394	394	217	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	38	44	73	1	16	1	1	395	10	10	4	1000	395	395	395	399	399
1004	394	3	0	0	0	45	0	0	1	383	2	12	12	16	25	1000	1000	1000	15274	0	394	394	217	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1038	6	1	39	43	73	1	16	1	1	397	10	10	7	1000	395	399	395	400	395
1004	398	3	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15037	0	394	398	221	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	38	43	73	1	16	1	1	395	10	10	7	1000	395	395	399	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	1	0	0	1	0	0	0	0	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616015	3341470	1	49	66955	70050	70050	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	1	0	0	2610	2	71	1	1	69798	30003	0	6	0	10000	30100	70038	70051	70048	70051	70051
40204	70050	525	0	0	0	0	0	1	0	1	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616175	3342206	1	49	66955	70050	70050	64631	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	2610	1	71	1	1	69798	30003	9	9	6	10000	30100	70036	70051	70036	70051	70051
40204	70050	525	0	0	0	0	0	1	0	1	0	70020	69781	59695	25	40104	30103	10001	30100	10000	616005	3341470	1	49	66970	70047	70035	64646	3	64953	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	0	2610	1	71	1	1	69813	30003	9	6	6	10000	30100	70051	70051	70051	70036	70051
40204	70035	525	0	0	0	0	0	1	0	1	0	70032	69781	59709	25	40100	30103	10001	30100	10000	616005	3342206	1	49	66970	70047	70050	64631	12	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	9	6	6	10000	30100	70048	70048	70048	70048	70051
40204	70050	524	0	0	0	0	0	1	0	0	0	70035	69764	59709	25	40104	30103	10000	30100	10000	616005	3342206	1	49	66955	70050	70050	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69813	30003	9	0	6	10000	30100	70036	70051	70051	70051	70036
40204	70035	524	0	0	0	0	0	0	0	0	0	70032	69781	59709	25	40100	30103	10001	30100	10000	616175	3342206	1	49	66970	70047	70047	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	0	0	0	2610	1	71	1	1	69813	30003	9	9	6	10000	30100	70051	70051	70036	70051	70056
40204	70035	525	0	0	0	0	0	2	0	1	0	70035	69781	59709	25	40100	30103	10001	30100	10000	616032	3342206	1	49	66970	70050	70050	64646	3	64938	40100	30200	10065	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	3	10000	1	1	0	2610	1	71	1	1	69798	30003	9	6	6	10000	30100	70036	70048	70036	70051	70056
40204	70050	524	0	0	0	0	0	1	0	0	0	70035	69781	59791	73	40113	30114	10001	30100	10000	616175	3342206	1	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	1	0	10000	1	1	0	2610	1	71	1	1	69810	30000	0	9	6	10000	30100	70036	70048	70048	70051	70051
40204	70050	524	0	0	0	0	0	0	0	0	0	70034	69786	59706	25	40100	30103	10000	30100	10000	616005	3342206	1	49	67056	70035	70050	64646	3	64953	40312	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	0	0	0	2610	1	71	1	1	69813	30003	0	0	9	10000	30100	70051	70051	70051	70051	70051
40204	70050	524	0	0	0	1	0	0	0	0	0	70035	69781	59706	25	40100	30103	10000	30100	10000	616005	3341470	1	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	0	1	0	2610	1	71	1	1	69813	30000	9	0	9	10000	30100	70048	70036	70051	70049	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	0	0	0	0	0	1	0	1	0	0	0	70039	69775	59713	25	40010	30013	10001	30010	10000	617068	3342398	0	49	66971	70054	70054	64653	3	64979	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2520	4	71	5	5	69814	30003	13	10	0	10000	30010	70055	70055	70055	70052	70036
40024	70051	525	0	0	0	0	0	0	0	1	1	0	0	70039	69778	59713	25	40014	30010	10001	30010	10000	616991	3342254	0	49	66980	70060	70060	64678	3	64985	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10001	0	1	1	10000	1	0	1	0	0	2520	4	71	4	4	69814	30003	13	13	0	10000	30010	70055	70055	70055	70055	70055
40024	70051	524	0	0	0	0	0	0	0	6	1	0	0	70020	69743	59713	25	40014	30010	10000	30010	10000	617018	3342398	1	49	66955	70054	70054	64672	3	64976	40010	30020	10000	60020	10000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2520	4	71	4	4	69817	30003	10	10	0	10000	30010	70055	70055	70052	70036	70036
40024	70054	525	0	0	0	0	1	0	0	1	0	0	0	70039	69778	59695	25	40014	30010	10001	30010	10000	617018	3342398	0	49	66963	70054	70035	64653	3	64979	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	1	1	0	2520	4	71	4	4	69804	30012	13	10	10	10000	30010	70058	70058	70042	70058	70061
40024	70041	524	1	0	0	0	0	0	0	1	1	0	0	70039	69778	59695	25	40014	30013	10001	30010	10000	616991	3342398	1	49	66980	70041	70060	64678	3	64985	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	1	1	10000	1	0	0	0	0	2520	4	71	6	4	69798	30000	0	13	13	10000	30010	70036	70055	70055	70036	70036
40024	70035	524	0	0	0	0	0	1	0	0	0	0	0	70020	69778	59695	25	40014	30013	10001	30010	10000	617018	3341470	0	49	66955	70035	70054	64653	3	64979	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	1	1	0	2520	4	71	4	4	69823	30003	13	10	13	10000	30010	70058	70061	70042	70061	70061
40024	70060	525	1	0	0	0	1	0	0	1	0	0	0	70039	69743	59710	25	40018	30013	10000	30010	10000	616991	3341470	0	49	66971	70035	70051	64669	3	64979	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	2	0	0	10000	1	0	1	0	0	2520	4	71	6	4	69817	30003	10	10	10	10000	30010	70240	70239	70057	70075	70055
40024	70244	525	0	0	0	1	0	0	0	1	0	0	0	70036	69778	59770	100	40038	30013	10007	30155	10000	621827	3342254	1	49	66974	70054	70051	64653	7	65066	40010	30020	10000	60020	10000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10002	0	3	1	10000	1	1	1	1	0	2520	4	71	4	5	69820	30006	10	0	13	10000	30010	70061	70061	70042	70058	70052
40024	70054	525	0	0	0	0	0	0	0	0	1	0	0	70039	69778	59695	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66974	70054	70054	64672	3	64979	40010	30020	10000	60020	10000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10004	1	1	1	10000	1	1	1	1	0	2520	4	71	4	4	69820	30006	10	10	13	10000	30010	70058	70066	70058	70169	70055
40024	70035	525	0	0	0	0	0	0	0	1	1	0	0	70039	69778	59716	25	40018	30013	10002	30010	10000	617072	3342686	0	49	66961	70060	70043	64659	3	64985	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10005	2	2	4671	10000	1	0	1	0	0	2520	3	71	4	5	69821	30012	13	13	0	10000	30010	70233	70059	70052	70058	70140

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6]
  ldrsw x0, [x6]
  ldrsw x0, [x6]
  ldrsw x0, [x6]
  ldrsw x0, [x6]
  ldrsw x0, [x6]
  ldrsw x0, [x6]
  ldrsw x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	201	1	0	1	0	1	0	0	65	1	0	3	26717	3	18	18	16	25	80100	100	80000	100	80016	500	1167733	49	23652	26733	26732	16736	6	16684	80116	200	80024	200	80024	26732	64	1	1	80201	100	99	100	80000	100	80000	0	100	80018	19	42	80057	1	1	59	80038	6	1	57	0	19	1	1	1	1	5118	2	16	2	1	26729	9	9	2	80000	100	26734	26734	26734	26734	26733
80204	26732	200	1	0	0	0	1	0	0	65	1	0	3	26722	2	18	18	16	25	80100	100	80000	100	80015	500	1169757	49	23634	26732	26714	16660	6	16685	80115	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80057	0	2	59	80038	6	1	57	42	19	0	1	1	1	5118	2	16	2	2	26730	9	9	0	80000	100	26733	26733	26734	26734	26733
80204	26714	200	1	0	1	0	0	1	0	65	1	0	3	26722	2	18	18	16	25	80100	100	80000	100	80015	500	1159191	49	23653	26732	26732	16660	6	16685	80116	200	80024	200	80024	26733	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80057	1	1	59	80038	6	1	57	0	19	1	1	1	1	5118	2	16	2	2	26729	9	9	2	80000	100	26733	26733	26733	26733	26715
80204	26732	200	1	0	1	0	1	0	0	65	1	0	1	26718	3	18	18	15	25	80100	100	80000	100	80016	500	1167095	49	23652	26714	26732	16660	6	16684	80115	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	42	80057	0	1	59	80038	6	1	57	42	19	1	1	1	1	5118	2	16	2	2	26729	9	9	2	80000	100	26716	26733	26733	26715	26734
80204	26733	200	1	0	0	0	1	0	0	66	0	0	3	26735	3	18	18	0	25	80100	100	80000	100	80015	500	1167763	49	23653	26732	26732	16660	6	16684	80116	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	0	80057	0	0	21	80038	6	1	57	42	19	1	1	1	1	5118	2	16	2	2	26729	9	9	2	80000	100	26733	26733	26715	26733	26733
80204	26732	200	1	0	0	0	1	0	0	65	1	0	3	26722	2	18	0	15	25	80100	100	80000	100	80016	500	1169757	49	23652	26732	26732	16660	6	16685	80115	200	80216	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	21	42	80057	1	0	59	80038	6	1	19	42	19	1	1	1	1	5118	2	16	1	3	26729	9	0	2	80000	100	26734	26733	26733	26733	26733
80204	26732	200	1	0	0	0	0	0	0	21	1	0	3	26722	2	18	18	16	25	80100	100	80000	100	80015	500	1169757	49	23652	26732	26732	16660	6	16666	80115	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	80057	1	0	59	80038	6	1	57	42	19	1	1	1	1	5118	2	16	2	2	26729	9	0	2	80000	100	26733	26733	26733	26733	26715
80204	26732	200	1	0	1	0	1	1	0	21	0	0	2	26721	2	18	18	19	25	80100	100	80000	100	80015	500	1179603	49	23653	26732	26732	16765	12	16902	80115	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	42	80057	1	0	59	80039	6	1	19	0	19	0	1	1	1	5118	2	16	2	2	26730	9	9	2	80000	100	26734	26733	26715	26733	26715
80204	26714	200	1	0	1	0	1	1	0	66	1	0	2	26717	2	18	0	0	25	80100	100	80000	100	80016	500	1169563	49	23652	26732	26732	16660	6	16666	80115	200	80024	200	80024	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80057	3	1	59	80039	6	1	57	42	19	0	1	1	1	5118	2	16	2	2	26730	9	9	0	80000	100	26715	26733	26733	26715	26715
80204	26732	200	1	0	1	0	0	0	0	65	1	0	3	26803	0	18	18	16	25	80100	100	80000	100	80015	500	1166836	49	23653	26732	26732	16660	6	16684	80116	200	80024	200	80024	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	42	80057	1	0	21	80038	6	0	19	42	19	0	1	1	1	5118	2	16	2	2	26729	9	9	2	80000	100	26733	26733	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	1	0	1	0	0	67	0	0	1	26729	0	0	12	0	25	80010	10	80000	10	80000	50	1168843	0	49	23628	26728	26727	16672	3	16707	80010	20	80000	20	80000	26708	85	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	43	0	80059	1	0	0	21	80040	6	1	59	43	19	1	5020	7	16	0	17	6	26725	0	10	4	80000	10	26728	26728	26728	26729	26729
80024	26708	200	0	0	0	0	1	45	0	0	2	26722	2	7	7	19	25	80010	10	80000	10	80000	50	1167791	0	49	23656	26737	26736	16681	3	16716	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	39	80039	6	0	0	43	0	0	5020	17	16	0	8	17	26733	13	13	0	80000	10	26737	26737	26737	26737	26716
80024	26737	200	1	0	0	0	0	21	0	0	1	26713	2	12	0	0	25	80010	10	80000	10	80000	50	1166896	0	49	23628	26708	26708	16672	9	16823	80010	20	80000	20	80000	26708	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80039	0	0	0	39	80039	6	1	0	0	0	0	5020	14	16	0	8	17	26725	10	14	4	80000	10	26728	26728	26709	26728	26729
80024	26728	200	0	0	0	0	0	45	1	0	1	26712	2	0	0	0	25	80010	10	80000	10	80000	50	1166886	1	49	23647	26708	26728	16672	3	16688	80010	20	80000	20	80000	26728	86	1	1	80021	10	9	10	80000	10	80000	0	10	80018	19	45	0	80059	1	0	0	61	80000	6	0	19	43	19	0	5020	14	16	0	17	7	26745	10	10	4	80000	10	26728	26709	26729	26729	26728
80024	26708	200	0	0	0	0	0	0	1	0	1	26713	2	12	12	0	25	80010	10	80000	10	80000	50	1166886	1	49	23628	26728	26728	16672	3	16707	80010	20	80000	20	80000	26728	86	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	39	80000	0	1	39	43	0	0	5020	17	16	0	8	17	26718	0	10	4	80000	10	26709	26728	26709	26729	26729
80024	26728	200	0	0	0	0	1	45	0	0	1	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23648	26727	26727	16672	3	16708	80010	20	80000	20	80000	26727	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	0	0	0	80039	6	1	0	44	0	0	5020	17	16	0	17	8	26749	10	10	0	80000	10	26709	26728	26729	26709	26709
80024	26708	200	0	0	0	0	0	45	0	0	1	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23628	26727	26708	16652	3	16708	80010	20	80000	20	80000	26728	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	0	80039	6	1	39	43	0	0	5020	8	16	0	17	17	26724	10	10	4	80000	10	26709	26728	26709	26729	26728
80024	26727	200	0	0	0	0	0	0	0	0	1	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23647	26708	26708	16672	10	16707	80010	20	80000	20	80000	26728	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80039	0	0	0	43	80039	6	1	0	0	0	0	5020	14	16	0	17	8	26733	13	13	5	80000	10	26737	26737	26716	26716	26737
80024	26714	200	1	0	0	0	0	67	1	0	1	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23647	26727	26728	16672	3	16707	80010	20	80000	20	80000	26708	85	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	0	80039	6	1	0	43	0	0	5020	17	16	0	17	17	26730	10	10	0	80000	10	26728	26709	26709	26729	26709
80024	26727	200	0	0	0	1	1	0	0	0	1	26713	2	0	12	0	25	80010	10	80000	10	80000	50	1166750	1	49	23648	26727	26727	16672	3	16707	80010	20	80000	20	80000	26727	85	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	43	0	80039	0	0	0	39	80039	0	1	39	43	0	0	5020	17	16	0	7	13	26745	13	0	0	80000	10	26716	26737	26737	26738	26715

LDRSW

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations