Firestorm: B.cc (taken) measurements

Code:

  b.ne .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3082	19	0	35	25	1000	1000	1000	5000	1	1960	1972	3	18	1000	1000	1000	1976	2046	1	1	1001	1000	1000	1000	1000	0	0	1846	559	958	479	482	1867	2033	1947	1983	2017	2005
1004	2044	15	0	35	25	1000	1000	1000	5000	1	1876	2000	3	18	1000	1000	1000	2018	2020	1	1	1001	1000	1000	1000	1000	0	0	1922	463	1020	445	484	2067	2037	1995	2111	1985	1973
1004	2092	15	0	35	25	1000	1000	1000	5000	1	2006	1820	3	18	1000	1000	1000	1944	2072	1	1	1001	1000	1000	1000	1000	0	0	1962	534	960	483	418	1973	2067	1975	1979	2067	1959
1004	2058	14	0	35	25	1000	1000	1000	5000	1	1954	2072	3	18	1000	1000	1000	2016	1894	1	1	1001	1000	1000	1000	1000	0	0	1962	517	930	494	471	1957	1983	1853	1961	1911	1971
1004	2052	14	0	35	25	1000	1000	1000	5000	1	1982	1926	3	18	1000	1000	1000	1960	1912	1	1	1001	1000	1000	1000	1000	0	0	1924	455	966	466	439	1939	1823	1987	1977	2065	1979
1004	2004	14	0	35	25	1000	1000	1000	5000	1	1870	2164	3	18	1000	1000	1000	2012	1986	1	1	1001	1000	1000	1000	1000	0	0	1980	520	938	425	466	1961	1985	1881	2027	1975	2063
1004	1974	15	0	35	25	1000	1000	1000	5000	1	1986	1966	3	18	1000	1000	1000	1832	1990	1	1	1001	1000	1000	1000	1000	0	0	1916	467	946	510	457	1991	1923	2011	1981	2039	2013
1004	1984	15	0	35	25	1000	1000	1000	5000	1	2070	1980	3	18	1000	1000	1000	1996	2046	1	1	1001	1000	1000	1000	1000	0	0	1958	479	920	463	482	1923	1981	1911	2039	2007	1911
1004	2028	14	0	35	25	1000	1000	1000	5000	1	2080	1970	3	16	1000	1000	1000	2008	2018	1	1	1001	1000	1000	1000	1000	0	0	1960	490	964	472	449	1985	1999	2005	2037	1905	1977
1004	2046	14	0	98	25	1000	1000	1000	5000	1	1938	2046	3	18	1000	1000	1000	2086	1996	1	1	1001	1000	1000	1000	1000	0	0	1938	414	974	465	464	1937	1961	2071	1977	1971	1877

Count: 8

Code:

  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0096

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	81169	605	0	0	0	0	0	0	218	27	80105	80105	80107	400629	1	49	77706	0	80772	80792	6	10	80107	80207	80207	80772	64730	1	1	80201	80100	80099	80100	100	80100	1	0	3	1	1	1	80747	422	671	314	319	80767	100	80773	80773	80775	80781	80775
80204	80764	604	0	0	0	0	12	0	70	27	80105	80105	80107	400629	0	49	77700	0	80792	80772	6	10	80107	80207	80207	80798	64730	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80753	339	705	316	321	80773	100	80777	80775	80777	80777	80775
80204	80772	605	0	0	0	0	0	0	28	27	80143	80124	80107	400629	1	49	77706	0	80768	80770	6	10	80107	80207	80207	80770	64742	4	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80747	314	647	316	313	80765	100	80761	80767	80771	80767	80767
80204	80774	605	0	0	0	0	0	0	28	27	80105	80105	80107	400629	0	49	77724	0	80782	80790	6	10	80107	80207	80207	80766	64720	1	1	80201	80100	80099	80100	100	80100	3	0	0	1	1	1	80753	312	643	313	318	80769	100	80763	80765	80777	80767	80767
80204	80934	606	0	0	0	0	12	0	28	27	80105	80105	80107	400629	1	49	77720	0	80802	80798	6	10	80107	80207	80207	80764	64722	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80743	316	657	318	325	80777	100	80765	81229	80813	80773	80767
80204	80760	605	0	0	0	0	0	0	28	27	80105	80105	80107	400629	1	49	77698	0	80796	80784	6	10	80107	80207	80207	80780	64734	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80749	320	651	315	319	80767	100	80775	80773	80773	80771	80777
80204	80776	605	0	0	0	0	0	0	28	27	80105	80105	80107	400629	0	49	77698	0	80774	80778	6	10	80107	80207	80207	80770	64728	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80755	316	651	309	317	80793	100	81118	80783	80769	80773	80773
80204	80768	605	0	0	0	0	0	0	28	27	80105	80105	80107	400629	0	49	77694	0	80764	80758	6	10	80107	80207	80207	80778	64752	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80753	319	655	315	315	80771	100	80769	80771	80769	80771	80775
80204	80784	605	0	0	0	0	0	0	28	27	80105	80105	80107	400629	0	49	77702	0	80780	80776	6	10	80107	80207	80207	80770	64746	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	1	1	80767	565	701	321	309	80773	100	80783	80769	80781	80779	80773
80204	80760	605	1	1	0	0	0	0	28	27	80105	80105	80107	400629	1	49	77692	0	80770	80768	6	10	80107	80207	80207	80782	64736	1	1	80201	80100	80099	80100	100	80100	0	0	0	1	4	1	80771	320	661	319	323	80775	100	80779	80781	80779	80781	80799

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	240093	1798	10	8	0	0	9	134	28	80011	80011	80012	400058	0	0	49	236486	0	240044	240044	6	10	80012	80022	80022	240048	240040	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240021	5	1	0	79842	160016	2	0	79971	80004	240041	0	0	10	240045	240048	240047	240047	240043
80024	240044	1798	7	7	0	0	9	133	28	80011	80011	80012	400058	1	9	49	236962	0	240044	240044	6	10	80012	80022	80022	240044	240042	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240019	8	2	0	80000	160016	0	0	79965	80002	240041	0	0	10	240045	240045	240045	240045	240045
80024	240044	1798	8	8	0	0	9	821	28	80011	80011	80012	400058	1	9	49	236962	3	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240021	8	2	0	80001	160014	0	0	79968	80001	240041	0	0	10	240045	239807	240043	240045	240045
80024	240044	1798	8	8	0	0	9	798	28	80011	80011	80012	400058	1	9	49	236964	0	240042	239655	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240021	8	2	0	80000	160016	0	0	79969	80002	240041	0	0	10	240045	240043	240045	240045	240045
80024	240044	1798	8	8	0	0	9	781	28	80011	80011	80012	400058	1	9	49	236964	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240021	8	2	0	80001	160016	0	0	79967	80002	240041	16	0	10	240045	240045	240043	239901	240045
80024	240044	1798	8	7	0	0	9	799	28	80011	80011	80012	400058	1	9	49	236964	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240021	8	2	0	80001	160016	0	0	79968	80002	240041	0	0	10	240009	240045	240045	240045	240045
80024	240044	1798	8	8	0	0	9	793	28	80011	80011	80012	400058	1	9	49	236964	0	240044	240044	6	10	80012	80022	80022	240042	240044	1	1	80021	80010	80009	80010	10	80010	0	3	1	1	1	240021	8	2	0	80001	160016	0	0	79969	80002	240041	0	0	10	240045	240045	240043	239964	240045
80024	240044	1798	8	8	0	0	9	793	28	80011	80011	80012	400058	1	9	49	236964	0	240044	240042	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	80010	10	80010	0	0	1	1	1	240021	8	2	0	80001	160016	0	0	79969	80002	240041	0	0	10	240043	240045	240045	240045	240045
80024	240044	1798	10	8	0	0	9	134	28	80011	80011	80012	400058	1	9	49	236964	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	80010	10	80010	0	0	1	4	1	240021	8	2	0	79999	160012	0	0	79969	80002	240262	0	0	10	240049	240043	240045	240037	240047
80024	240050	1798	8	6	0	0	11	149	41	80011	80011	80012	400058	1	9	49	236964	0	240044	240044	6	10	80012	80022	80054	240044	240044	1	1	80021	80010	80009	80010	10	80010	1	0	1	1	1	240021	8	2	0	80001	160016	0	0	79970	80002	240041	0	0	10	240043	240045	240045	239876	240043

B.cc (taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations