Firestorm: MADD (64-bit) measurements

Code:

  madd x0, x0, x1, x2

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	22	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	3	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	82	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	451	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	103	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	82	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	383	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	105	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  madd x0, x0, x1, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	1	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	81	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30207	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10145	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	251	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	1118	662	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  madd x0, x1, x0, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3a	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	224	0	0	0	0	0	468	19922	30017	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	30017	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10046	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	279	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	442	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10264	30200	30033	374	1	1	10201	100	99	100	10100	100	0	18	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	189	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	0	0	435	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	193	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	424	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	145	19922	0	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	662	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	890	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	5	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	834	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	853	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	889	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	884	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30071	30034
10024	30033	225	0	950	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	2	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	871	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	829	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	798	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 4: Latency 1->4

Code:

  madd x0, x1, x2, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10040	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	339	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10148	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	93	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	69	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10202	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	76	15	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10068	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	90	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	75	0	0	0	0	0	904	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	76	0	0	0	0	0	48	25	10010	10033	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	69	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	540	25	10010	10032	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10084	164	1	1	10021	10	9	10	10010	10	2	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	1	1	1	1	0	48	25	10010	10010	10010	70204	0	49	6957	10037	10085	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	48	25	10010	10033	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	2	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	214	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	3	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038

Test 5: throughput

Count: 8

Code:

  madd x0, x8, x9, x9
  madd x1, x8, x9, x9
  madd x2, x8, x9, x9
  madd x3, x8, x9, x9
  madd x4, x8, x9, x9
  madd x5, x8, x9, x9
  madd x6, x8, x9, x9
  madd x7, x8, x9, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80035	599	0	0	0	0	0	0	15	0	0	35	25	80100	80100	80100	400500	49	76955	80035	80035	69971	0	6	69989	80100	80208	240224	80035	164	1	1	80201	100	99	100	80100	100	0	1	0	0	1	1	1	5117	3	16	1	1	80032	80000	80100	80309	80036	80126	80036	80036
80204	80035	599	0	0	0	1	1	0	0	0	0	35	25	80100	80100	80100	400500	49	76955	80035	80035	69971	0	6	69989	80100	80208	240224	80035	164	1	1	80201	100	99	100	80100	100	0	1	0	0	1	1	1	5117	1	16	1	1	80032	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	60	0	0	46	25	80100	80100	80100	400500	49	76955	80035	80035	69964	0	20	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	16	3	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	1	2	0	3	4	36	0	0	46	47	80100	80100	80100	400500	49	76955	80173	80171	70015	0	11	70124	80188	80331	240406	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	16	3	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	49	76955	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	49	76955	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	16	2	3	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	49	76955	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	49	76955	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	16	3	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	49	76955	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	3	16	2	3	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	0	0	711	25	80100	80100	80100	400500	49	75560	80035	80035	69964	0	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	12	0	0	0	0	5110	3	16	3	2	80031	80000	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	80074	599	0	0	0	0	0	0	0	0	0	466	0	41	80010	80010	80010	400157	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	12	16	6	4	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	46	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	6	16	6	5	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	46	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	5	16	9	4	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	0	0	0	0	155	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	12	0	0	0	5020	12	16	11	5	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	711	0	25	80010	80010	80010	400050	0	0	49	76955	80074	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	5	16	4	6	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	616	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	4	16	5	12	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	711	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	3	16	9	5	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	0	0	0	0	711	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	10	16	5	4	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	357	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	3	16	4	5	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	0	46	0	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	5	16	5	11	80032	80000	0	80010	80036	80036	80036	80036	80036

MADD (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations