Firestorm: LDRSB (post-index, 32-bit) measurements

Code:

  ldrsb w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	7	1	1	1	0	1	68	0	0	0	0	1	0	1025	19	0	4	0	21	25	2000	1000	1000	1000	1000	52840	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1027	8	0	52	1048	1	0	11	12	16	1040	51	5	23	64	7	1	0	73	1	16	1	1	1037	1000	31	40	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	1	47	24	0	0	0	1	0	1025	6	1	1	0	12	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1008	8	0	64	1044	3	0	20	32	21	1012	30	5	21	56	7	1	0	73	1	16	1	1	1037	1000	43	23	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	2	0	0	71	16	2	0	0	3	0	1025	0	0	0	2	16	25	2000	1000	1000	1000	1000	52840	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1017	8	0	56	1027	1	0	25	0	18	1012	30	5	15	56	7	40	0	73	1	16	1	1	1037	1000	37	37	1000	1000	1047	1047	1041	1041	1041
2004	1040	8	1	1	2	1	0	80	12	1	0	0	1	0	1025	16	0	1	1	17	25	2000	1000	1000	1000	1000	52840	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1023	7	1	37	1028	1	0	27	0	20	1008	42	4	18	56	7	2	4	73	1	16	1	1	1037	1000	31	40	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	0	0	55	0	0	0	0	1	12	1040	0	0	0	0	16	25	2000	1000	1000	1000	1000	52848	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1021	7	0	33	1029	12	0	0	12	15	1020	36	5	20	56	6	0	0	73	1	16	1	1	1037	1000	30	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	72	14	1	0	0	1	0	1025	9	0	2	2	13	25	2000	1000	1000	1000	1000	52828	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1021	7	0	41	1049	3	0	12	10	16	1014	36	4	24	40	7	11	0	73	1	16	1	1	1037	1000	28	29	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	39	9	1	0	0	2	0	1025	8	0	1	0	15	25	2000	1000	1000	1000	1000	52840	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1024	6	0	57	1054	1	0	23	12	17	1029	36	5	20	56	7	1	0	73	1	16	1	1	1036	1000	31	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	1	0	0	0	83	12	2	0	0	2	0	1025	8	0	0	0	11	25	2000	1000	1000	1000	1000	52840	45824	1	1043	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1052	7	0	57	1036	1	0	21	6	18	1031	30	4	21	56	7	0	0	73	1	16	1	1	1037	1000	31	27	1000	1000	1043	1041	1041	1041	1041
2004	1040	7	1	1	2	0	0	47	14	0	0	1	1	4	1025	0	0	4	2	11	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1043	7	1	42	1035	6	1	26	6	21	1040	36	5	22	40	6	2	0	73	1	16	1	1	1037	1000	29	32	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	2	2	0	0	47	14	1	0	0	0	0	1025	13	1	0	0	11	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	791	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1027	20	0	48	1027	4	0	20	12	26	1024	30	5	19	56	6	1	0	73	1	16	1	1	1037	1000	29	29	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1885

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	71861	539	0	0	0	0	0	437	819	1	696	80	71833	793	3	2	71557	25	50715	40580	10126	40100	10000	613567	2725286	49	68690	72004	71729	65214	3	65517	50100	40200	10000	70200	10000	71932	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10878	141	487	10611	269	16	902	132	60	10909	115	2	121	0	0	5	2610	7	57	2	2	71846	40536	1033	1166	1073	10000	40100	71918	71759	71687	71949	71951
50204	71785	538	0	1	1	1	1	412	809	1	688	104	71840	776	3	2	71759	25	50720	40612	10129	40100	10000	613698	2722913	49	68844	71937	71841	65287	3	65553	50100	40200	10000	70200	10000	71831	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10890	152	559	10620	273	9	884	84	29	10891	119	2	125	0	0	4	2610	2	58	2	2	71823	40496	1047	1041	952	10000	40100	71960	71882	71839	71838	71930
50204	71898	538	0	0	0	1	0	488	793	1	704	96	71831	766	3	2	71689	25	50735	40628	10128	40100	10000	614129	2722399	49	68961	71867	71983	65245	3	65509	50100	40200	10000	70200	10000	71883	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10870	128	467	10622	252	7	866	32	23	10888	123	3	119	0	0	5	2610	2	58	2	2	71669	40488	1004	1036	1025	10000	40100	71947	72057	71850	71953	71979
50204	71809	539	0	0	0	1	0	451	786	1	688	140	71800	781	2	2	71632	25	50670	40660	10128	40100	10000	614196	2727592	49	68753	71769	71962	65339	3	65449	50100	40200	10000	70200	10000	71907	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10910	131	477	10614	270	10	893	28	27	10910	137	2	131	0	3	5	2610	2	58	2	2	71651	40480	1052	963	1108	10000	40100	71883	71759	71994	71813	72055
50204	71835	539	0	0	0	0	0	340	796	1	672	96	71921	819	3	2	71474	25	50750	40632	10125	40100	10000	614568	2727965	49	68683	71815	71931	65157	3	65685	50100	40200	10000	70200	10000	71706	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10888	156	503	10614	263	12	866	32	20	10925	131	2	128	0	3	6	2610	2	58	2	2	71326	40540	1047	1046	1035	10000	40100	71938	71944	71850	72021	71902
50204	72084	538	0	0	0	1	0	448	808	1	696	144	72029	817	2	2	71697	25	50720	40604	10120	40100	10000	612027	2719233	49	68910	71795	71851	65350	3	65438	50100	40200	10000	71362	10000	71834	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10870	172	506	10623	258	7	926	72	1865	10922	110	1	125	0	0	3	2610	2	58	2	2	71746	40560	1087	1030	1063	10000	40100	71993	71856	71765	71822	71811
50204	71757	539	0	0	0	0	0	489	782	1	704	96	72005	771	2	2	71637	25	50780	40624	10126	40100	10000	613431	2728033	49	68764	71947	71773	65204	3	65599	50100	40200	10000	70200	10000	72025	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10886	127	500	10667	278	12	902	38	18	10916	116	2	135	0	3	7	2610	2	58	2	2	71659	40528	1008	1081	1114	10000	40100	71906	71868	71800	71952	71842
50204	71854	538	0	0	0	0	0	476	824	1	696	96	71664	814	2	2	71457	25	50730	40592	10139	40100	10000	613310	2729251	49	68929	71789	71876	65346	3	65663	50100	40200	10000	70200	10000	71885	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10938	140	505	10611	278	10	902	122	23	10916	117	2	124	0	0	11	2610	2	58	2	2	71819	40432	1061	1004	1092	10000	40100	71863	71821	71861	71955	71991
50204	71991	537	0	0	0	0	1	426	784	1	704	100	71995	779	2	2	71541	25	50815	40568	10128	40100	10000	613670	2723330	49	68769	71988	71742	65309	3	65559	50100	40200	10000	70200	10000	71751	35	1	1	40202	100	99	100	10000	30100	10000	0	100	10926	163	488	10632	249	12	894	64	23	10899	131	2	123	0	0	5	2610	2	57	2	2	71591	40504	1018	984	1102	10000	40100	72057	72005	71934	71928	71958
50204	71714	538	0	0	0	1	0	495	803	1	728	100	71711	768	4	2	71505	25	50760	40564	10124	40100	10000	614331	2720845	49	68823	71811	71791	65292	3	65615	50100	40200	10000	70200	10000	71775	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10833	150	499	10597	270	13	878	72	20	10908	131	3	120	0	3	4	2610	2	58	2	2	71595	40496	1069	1060	1020	10000	40100	71829	72059	72115	71960	71899

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1942

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72235	540	3	0	0	0	0	0	436	838	1	704	3	108	71845	803	6	2	71875	25	50745	40594	10138	40010	10000	613473	2728116	0	49	68821	71792	71856	65421	3	65769	50010	40020	10000	70020	10000	71948	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10920	4	191	521	10678	257	10	905	76	35	10903	138	7	134	5	0	3	0	2520	9	85	4	2	71842	40536	1082	1003	1073	10000	40010	72067	72077	72503	71907	72052
50024	71954	539	4	0	0	0	1	0	425	810	1	704	4	124	71952	785	8	2	71936	25	50705	40586	10148	40160	10000	613585	2725003	0	49	68862	71964	71862	65471	3	65713	50010	40020	10000	70020	10000	71964	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10905	10	168	499	10667	286	11	916	124	28	10927	133	9	120	5	0	3	0	2520	2	85	2	5	71731	40600	1086	1003	986	10000	40010	72090	71894	72049	72077	71999
50024	71971	558	5	0	0	0	0	0	417	810	1	712	3	108	72045	801	6	3	71925	25	50655	40498	10137	40010	10000	614323	2724651	1	49	68944	71991	72065	65380	3	65493	50010	40020	10000	70020	10000	72065	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10899	3	154	507	10648	256	10	907	78	31	10904	125	8	121	3	0	7	0	2520	4	85	4	2	71721	40540	1130	1089	1070	10000	40010	72042	71815	72150	72119	71998
50024	71879	538	3	0	0	0	0	0	446	837	1	712	2	108	71964	787	5	2	71796	37	50745	40558	10144	40010	10000	612647	2726713	0	49	68900	71860	71994	65342	3	65674	50010	40020	10000	70020	10000	71820	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10899	4	175	516	10640	251	7	912	78	36	10907	131	8	133	4	6	4	0	2520	2	85	2	5	71761	40544	1083	1124	1057	10000	40010	72029	71989	72152	71962	72139
50024	71935	539	4	0	0	0	0	0	410	826	1	712	4	120	72078	809	5	3	71705	25	50645	40586	10137	40010	10000	613052	2728004	0	49	68896	72037	72088	65492	3	65612	50010	40020	10000	70020	10000	71962	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10907	8	185	504	10652	273	12	899	32	35	10913	124	11	131	4	0	3	0	2520	2	85	4	4	71841	40560	1112	1051	1068	10000	40010	71983	72107	71828	72058	71766
50024	71741	539	4	0	0	0	0	0	410	797	1	712	3	116	71912	838	5	3	71889	25	50645	40502	10140	40010	10000	613123	2732062	0	49	68819	72113	72112	65503	3	65717	50010	40020	10000	70020	10000	72097	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10908	4	189	520	10636	259	8	904	72	30	10916	121	10	141	4	0	4	0	2520	4	85	2	4	71711	40548	1067	1074	1070	10000	40010	72085	72069	72025	72059	71895
50024	72100	538	4	0	1	0	0	0	404	834	1	728	4	120	72014	789	6	2	72060	25	50780	40586	10142	40010	10000	614473	2723804	0	49	68903	71908	72137	65277	3	65579	50010	40020	10000	70020	10000	71966	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10932	4	191	499	10654	265	8	908	156	55	10923	132	9	119	4	0	3	0	2520	3	85	3	5	71650	40548	1123	1063	926	10000	40010	71975	71980	71830	72009	71900
50024	71876	539	4	0	0	0	0	0	364	816	1	728	4	116	72099	779	4	2	72021	25	50785	40586	10126	40010	10000	613952	2720598	0	49	68567	72040	72016	65428	3	65763	50010	40020	10000	70020	10000	71926	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10905	5	179	550	10670	228	8	894	68	35	10912	126	7	127	4	0	4	0	2520	4	85	4	3	71949	40560	1110	1049	1112	10000	40010	72188	72063	72094	71969	72048
50024	71839	538	4	0	0	0	0	0	478	806	1	744	4	116	71876	814	7	2	71728	25	50685	40590	10136	40010	10000	614416	2729061	0	49	68733	71894	71898	65357	3	65586	50010	40020	10000	70020	10000	72056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10893	4	161	524	10648	270	9	901	76	20	10920	135	8	142	4	5	11	0	2520	4	85	4	4	71773	40540	1141	1049	1167	10000	40010	72010	71751	72132	71964	72008
50025	72043	539	3	0	0	0	0	0	383	831	1	688	3	116	71975	809	5	2	71864	25	50680	40590	10147	40010	10000	614078	2734425	0	49	69000	71886	72023	65500	3	65579	50010	40020	10000	70020	10000	71938	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10909	3	183	483	10652	250	11	926	74	29	10901	116	7	147	2	0	8	0	2520	4	85	4	2	71676	40520	1065	1125	1203	10000	40010	71852	72037	71995	71954	71907

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6], #8
  ldrsb w0, [x7], #8
  ldrsb w0, [x8], #8
  ldrsb w0, [x9], #8
  ldrsb w0, [x10], #8
  ldrsb w0, [x11], #8
  ldrsb w0, [x12], #8
  ldrsb w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3683

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	30023	221	3	0	0	0	0	8106	829	1	752	124	92	29525	754	723	1847	1957	2178	25	160195	80174	80000	80120	80017	400860	1297330	1	63	49	26460	29437	29486	9437	6	9671	160143	80224	80020	80224	80020	29243	35	1	1	80201	100	99	31	100	80000	100	80000	0	100	80946	33	364	5629	85432	606	13	902	50	6017	86586	876	146	5252	5102	53	3	3	1	1	1	5117	1	16	0	3	29342	32	80066	619	637	112	80000	80100	29370	29420	29527	29407	29728
160204	29583	222	2	0	0	0	0	8222	837	1	672	110	136	29385	803	720	1662	1777	2209	25	160170	80179	80000	80120	80016	400898	1303251	1	63	49	26409	29226	29291	9463	6	9511	160135	80392	80020	80220	80020	29403	35	1	1	80201	100	99	26	100	80000	100	80000	0	100	80892	36	362	5879	85420	655	10	902	92	5685	86547	703	125	5671	5284	32	0	3	1	1	1	5117	1	16	1	2	29736	24	80079	586	617	134	80000	80100	29650	29726	29368	29431	29621
160204	29400	222	3	3	0	3	0	7155	842	1	656	120	156	29283	763	639	1660	1792	2282	25	160178	80166	80000	80120	80015	400935	1300687	1	74	49	26277	29480	29448	9478	6	9527	160134	80220	80020	80224	80024	29607	35	1	1	80201	100	99	22	100	80000	100	80000	0	100	80979	54	390	5434	85662	686	13	923	100	4768	86735	746	113	5779	5067	55	12	1	1	1	1	5117	1	16	1	5	29760	36	80073	564	549	97	80000	80100	29545	29460	29436	29487	29165
160204	29621	222	2	0	0	0	0	7880	830	1	744	115	144	29392	746	591	1797	1984	2135	25	160182	80177	80000	80124	80014	400871	1292286	1	59	49	26450	29495	29340	9586	6	9335	160134	80224	80024	80224	80024	29451	35	1	1	80201	100	99	25	100	80000	100	80000	0	100	80922	32	400	5146	85925	649	10	887	34	5308	86310	792	135	5779	4853	32	0	3	1	1	1	5117	3	16	3	1	29477	29	80074	477	529	101	80000	80100	29424	29463	29341	29507	29550
160204	29375	221	2	0	0	2	0	8272	830	1	696	117	104	29298	768	670	1946	1847	2038	25	160170	80185	80000	80124	80017	400904	1302727	0	64	49	26242	29473	29149	9317	6	9600	160136	80224	80024	80220	80024	29303	35	1	1	80201	100	99	20	100	80000	100	80000	0	100	80972	72	354	6155	86245	666	19	899	30	5668	86406	778	130	5647	5053	72	1	3	1	1	1	5117	2	16	1	2	29584	27	80076	526	541	108	80000	80100	29623	29442	29520	29482	29194
160204	29531	223	3	3	0	3	0	7345	802	1	696	96	96	29220	758	654	1798	1790	2175	25	160186	80179	80000	80120	80014	400816	1298573	1	75	49	26233	29516	29291	9315	6	9417	160135	80224	80020	80224	80020	29414	35	1	1	80201	100	99	27	100	80000	100	80000	0	100	80950	48	355	5412	86190	632	13	900	66	5027	86011	762	124	5540	5064	69	0	3	1	1	1	5117	1	16	2	0	29405	17	80069	628	504	118	80000	80100	29547	29476	29545	29420	29381
160204	29371	220	3	0	0	0	0	8216	821	1	664	122	112	29459	819	600	1746	1994	2219	25	160171	80166	80000	80292	80012	400843	1302501	0	54	49	26187	29567	29464	9509	6	9539	161518	80220	80020	80220	80024	29291	35	1	1	80201	100	99	36	100	80000	100	80000	0	100	80947	36	375	5967	85956	653	14	899	50	5207	86576	810	125	5763	4677	17	3	0	1	1	1	5117	2	16	0	2	29622	23	80073	551	598	102	80000	80100	29718	29553	29360	29538	29539
160204	29414	221	2	0	0	0	0	7952	795	1	664	113	132	29407	810	394	1559	2000	2173	25	160177	80178	80000	80124	80013	400862	1290878	0	81	49	26362	29467	29475	9221	6	9406	160141	80224	80024	80224	80024	29411	35	1	1	80201	100	99	33	100	80000	100	80000	0	100	80966	55	359	5878	85276	675	11	866	44	6001	86454	850	121	5595	4610	52	0	3	1	1	1	5117	0	16	1	2	29561	29	80075	527	556	109	80000	80100	29617	29469	29439	29310	29180
160204	29348	219	4	0	0	0	0	8164	832	1	688	120	124	29446	804	638	1866	1830	2086	25	160180	80172	80000	80120	80015	400902	1299708	1	61	49	26398	29602	29668	9401	6	9535	160133	80228	80020	80220	80020	29552	35	1	1	80201	100	99	38	100	80000	100	80000	0	100	80967	69	388	5869	85362	636	12	894	78	6027	86072	790	136	5429	4271	73	5	6	1	1	1	5117	2	16	0	3	29395	23	80081	603	539	106	80000	80100	29178	29501	29576	29694	29188
160204	29637	220	2	0	0	0	0	7469	789	1	688	111	148	29451	797	534	1603	1874	2125	25	160172	80173	80000	80120	80015	400833	1303258	1	64	49	26687	29622	29434	9406	6	9357	160141	80220	80020	80220	80020	29422	35	1	1	80201	100	99	29	100	80000	100	80000	0	100	80918	36	347	5616	85259	653	14	898	42	5520	86389	684	127	5021	4906	33	0	3	1	1	1	5117	0	16	0	2	29337	33	80082	589	595	141	80000	80100	29254	29561	29517	29531	29588

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3641

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29727	219	1	0	0	0	0	6793	0	790	1	680	94	136	29260	831	377	1754	2143	2016	25	160071	80059	80000	80010	80000	400305	1282146	0	45	49	26042	29080	29197	9257	0	3	9002	160010	80020	80000	80020	80000	29122	35	1	1	80021	10	9	9	10	80000	10	80000	1	10	80888	0	483	5706	0	85266	749	14	889	172	5113	86022	763	127	5152	4855	0	3	3	0	5020	5	16	0	2	2	29215	42	80065	402	361	84	80000	80010	29276	29474	29508	29268	29141
160024	29203	218	0	0	0	0	0	6382	0	791	1	728	96	108	29190	785	357	1850	2065	1947	25	160064	80074	80000	80010	80000	400345	1288476	0	56	49	26003	29273	29308	9173	0	3	9101	160010	80020	80000	80020	80000	29263	35	1	1	80021	10	9	13	10	80000	10	80000	0	10	80917	19	516	5606	0	85092	663	9	880	48	4655	85967	751	119	4700	4980	0	0	3	0	5020	6	16	0	2	2	29156	40	80061	376	335	81	80000	80010	29085	29002	29345	29363	29127
160024	28910	218	0	0	0	0	0	6764	0	792	1	624	77	80	29308	761	370	1850	2114	1809	25	160066	80075	80000	80010	80000	400310	1292202	0	71	49	25973	29309	29337	9304	0	3	9317	160010	80020	80000	80020	80000	29119	35	1	1	80021	10	9	4	10	80000	10	80000	0	10	80916	18	515	6057	0	85736	727	11	908	50	4907	86357	773	106	4943	5110	18	0	4	0	5020	2	16	0	6	2	29291	39	80053	343	349	95	80000	80010	29063	29124	29339	29553	29451
160024	29047	217	0	0	0	0	0	6933	0	769	1	688	90	100	29147	739	380	1913	1888	1924	25	160066	80059	80000	80010	80000	400318	1284557	1	65	49	26184	29126	28915	9015	0	3	9030	160010	80020	80000	80020	80000	29289	35	1	1	80021	10	9	14	10	80000	10	80000	0	10	80865	0	463	5785	0	85222	694	12	928	42	5627	85731	824	111	5080	5133	18	3	5	0	5020	2	16	0	2	3	29068	40	80054	288	365	101	80000	80010	29315	29162	29591	29372	29080
160024	29042	218	0	0	0	0	0	6585	0	784	1	680	92	136	29046	796	371	1871	2146	1874	25	160077	80062	80000	80010	80000	400310	1287308	1	68	49	26076	29201	28963	9246	0	3	9249	160010	80020	80000	80020	80000	29342	35	1	1	80021	10	9	15	10	80000	10	80000	0	10	80871	18	517	6042	0	85195	675	13	857	46	4558	85954	686	125	5118	4553	0	3	0	0	5020	2	16	0	6	6	29102	33	80058	389	325	76	80000	80010	29305	29137	29314	29418	29312
160024	29241	218	1	0	1	0	0	6645	0	805	1	736	107	100	29244	815	387	2270	2075	1945	25	160070	80075	80000	80010	80000	400381	1283764	0	49	49	26085	29307	29132	8939	0	3	9084	160010	80020	80000	80020	80000	29141	35	1	1	80021	10	9	8	10	80000	10	80000	0	10	80863	19	485	5676	0	84845	699	9	902	50	5852	85443	788	122	4938	4857	36	0	0	0	5020	2	16	0	3	2	29350	29	80041	341	302	99	80000	80010	29015	29044	29549	29229	29380
160024	29127	218	1	0	0	1	0	6887	0	764	1	720	81	144	29111	747	395	1848	2016	1730	25	160061	80075	80000	80010	80000	400294	1287870	0	69	49	26291	29171	29157	9158	0	3	9317	160010	80020	80000	80020	80000	29337	35	1	1	80021	10	9	18	10	80000	10	80000	0	10	80926	37	545	5893	0	85216	707	11	897	54	4876	85592	711	132	5235	4262	19	3	0	0	5020	2	16	0	2	2	29118	33	80063	369	363	95	80000	80010	29166	29144	29552	29245	29325
160024	29003	219	2	1	1	1	0	6514	0	776	1	744	95	156	29247	776	379	2078	2174	1948	25	160064	80078	80000	80010	80000	400310	1297187	0	56	49	25901	29159	29225	8922	0	3	9019	160010	80020	80000	80020	80000	29154	35	1	1	80021	10	9	10	10	80000	10	80000	0	10	80882	19	457	5223	0	85643	742	12	863	36	5623	85445	747	133	4868	4484	35	0	3	0	5020	2	16	0	2	2	29250	24	80078	338	334	85	80000	80010	29493	29051	29459	29253	28986
160024	29016	219	1	1	0	0	0	6822	0	806	1	680	92	136	29118	743	352	1854	2035	1931	25	161297	80059	80000	80010	80000	400306	1281189	0	64	49	25756	29073	29000	9128	0	3	9137	160010	80020	80000	80020	80000	29083	35	1	1	80021	10	9	9	10	80000	10	80000	0	10	80862	0	490	5488	0	84975	699	17	859	42	5503	85933	710	115	5038	4935	0	0	4	0	5020	3	16	0	2	6	29048	44	80054	349	352	95	80000	80010	29115	29291	29454	29239	29259
160024	29112	216	1	0	1	0	0	6725	0	804	1	712	102	104	29266	797	372	2058	2193	1798	25	160072	80068	80000	80010	80000	400352	1282600	0	58	49	26017	28994	29083	9111	0	3	8854	160010	80020	80000	80020	80000	29050	35	1	1	80021	10	9	17	10	80000	10	80000	0	10	80877	0	470	6612	0	85206	711	11	886	42	4892	85999	732	133	5062	4831	37	2	3	0	5020	2	15	0	3	2	29382	31	80055	411	359	79	80000	80010	29393	29368	29510	29270	29304

LDRSB (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations