Firestorm: LDRSH (pre-index, 32-bit) measurements

Code:

  ldrsh w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	23	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1054	8	0	0	0	159	0	0	0	1	24	1035	11	116	36	1	43	25	2000	1000	1000	1000	1000	52804	45832	1	1040	1040	702	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1010	6	0	39	1152	0	0	12	0	114	1153	43	8	115	47	0	73	1	16	1	1	1037	1000	36	35	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	1	144	0	0	0	1	0	1025	16	99	18	22	34	25	2000	1000	1000	1000	1000	52792	45831	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1016	0	0	54	1126	6	0	12	6	118	1137	42	6	121	55	0	73	1	16	1	1	1036	1000	33	38	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	155	0	0	0	6	0	1025	0	101	3	5	32	25	2000	1000	1000	1000	1000	52808	45827	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1010	6	0	53	1134	7	0	20	12	114	1125	30	5	114	47	0	73	1	16	1	1	1032	1000	33	31	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	152	18	0	0	3	0	1025	17	106	9	16	31	25	2000	1000	1000	1000	1000	52808	45831	1	1040	1040	700	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	55	1116	0	0	0	0	124	1116	30	6	122	31	0	73	1	16	1	1	1036	1000	34	31	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	160	18	1	0	5	0	1025	17	98	12	0	39	25	2000	1000	1000	1000	1000	52792	45832	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	0	0	44	1114	10	0	16	8	113	1127	24	5	115	47	0	73	1	16	1	1	1037	1000	31	38	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	182	12	0	0	4	0	1025	10	105	6	15	35	25	2000	1000	1000	1000	1000	52796	45831	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1028	0	3	71	1127	3	0	30	12	114	1128	30	7	125	55	0	73	1	16	1	1	1033	1000	43	37	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	144	0	0	0	4	0	1025	4	92	2	2	31	25	2000	1000	1000	1000	1000	52808	45830	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	6	0	47	1124	12	0	20	12	117	1137	48	6	116	55	0	73	1	16	1	1	1037	1000	27	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	1	0	151	0	1	0	6	0	1025	0	99	4	0	36	25	2000	1000	1000	1000	1000	52828	45829	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1014	0	0	65	1136	3	0	26	12	123	1139	30	5	117	55	0	73	1	16	1	1	1034	1000	33	34	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	148	15	1	0	4	20	1025	11	105	2	0	41	25	2000	1000	1000	1000	1000	52820	45829	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1016	0	0	64	1157	0	0	16	6	117	1142	40	5	132	71	0	73	1	16	1	1	1036	1000	47	31	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	143	16	0	0	3	0	1025	0	108	10	1	39	25	2000	1000	1000	1000	1000	52824	45831	1	1040	1040	700	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	0	1	39	1127	0	0	14	0	114	1120	42	6	115	31	0	73	1	16	1	1	1037	1000	33	32	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1728

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	20	22	29	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72121	540	1	0	0	0	688	0	803	1	736	100	71927	804	1	1	71282	25	50830	40636	10111	40100	10000	676103	2718254	1	49	68769	71672	71589	64938	3	65321	50100	40200	10000	70200	10000	71500	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10888	150	497	10619	271	10	922	50	31	10894	123	1	121	3	3	2610	2	51	1	1	71285	40496	936	900	823	10000	40100	71680	71742	71615	71585	71661
50204	71709	536	1	0	0	0	589	0	805	1	736	120	71636	816	1	1	71412	25	50695	40636	10115	40100	10000	677786	2704829	1	49	68511	71695	71901	65158	3	65428	50100	40200	10000	70200	10000	71515	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10943	154	491	10651	270	8	912	52	37	10915	125	1	129	0	10	2610	1	51	1	1	71300	40512	822	772	972	10000	40100	71885	71654	71609	71647	71838
50204	71734	538	0	0	0	0	628	0	801	1	680	108	71728	815	1	1	71419	25	50645	40568	10128	40100	10000	677894	2717696	1	49	68587	71777	71710	65182	3	65239	50100	40532	10000	70200	10000	71928	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10920	154	531	10626	259	7	935	80	34	10923	121	1	111	0	7	2610	1	51	1	1	71516	40468	807	872	914	10000	40100	71660	71675	71702	71519	71556
50204	71859	538	1	0	0	0	634	0	792	1	776	100	71528	733	1	1	71496	25	50695	40584	10120	40100	10000	675128	2710475	1	49	68613	71836	71717	65178	3	65297	50100	40200	10000	70200	10000	71640	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10905	159	513	10613	276	12	923	52	31	10926	133	1	124	3	7	2610	1	51	1	1	71579	40504	920	924	959	10000	40100	71706	71597	71648	71739	71615
50204	71625	538	0	0	0	0	568	0	793	1	744	100	71626	799	1	1	71481	25	50690	40572	10119	40100	10000	676589	2709170	1	49	68743	71763	71530	65002	3	65372	50100	40200	10000	70200	10000	71676	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10928	156	524	10611	233	10	918	126	40	10890	126	1	113	3	18	2610	1	51	1	1	71359	40544	790	786	853	10000	40100	71786	71727	71848	71712	71486
50204	71495	537	0	0	0	0	578	0	787	1	680	132	71486	782	1	1	71308	25	50764	40588	10118	40100	10000	677494	2718949	1	49	68580	71694	71696	65242	3	65390	50100	40200	10000	70200	10000	71593	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10887	169	515	10666	275	13	923	74	46	10890	129	1	128	17	3	2610	1	51	1	1	71732	40484	914	914	935	10000	40100	71586	71577	71696	71658	71854
50204	71470	538	0	1	0	0	535	0	796	1	752	132	71619	826	1	1	71421	25	50675	40608	10133	40100	10000	675298	2703607	1	49	68517	71566	71694	65015	3	65421	50100	40200	10000	70200	10000	71694	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10872	154	507	10648	267	10	881	74	44	10892	118	1	138	0	3	2610	1	51	1	1	71608	40468	1010	978	829	10000	40100	71692	71635	71642	71775	71709
50204	71537	537	0	0	0	0	597	0	811	1	680	104	71586	778	1	2	71334	25	50770	40568	10140	40100	10000	677885	2709110	1	49	68639	71641	71639	65155	3	65259	50100	40200	10000	70200	10000	71777	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10906	141	492	10628	276	47	932	28	28	10902	122	1	137	3	4	2610	1	51	1	1	71603	40500	934	788	871	10000	40100	71481	71695	71596	71672	71717
50204	71546	537	0	0	0	0	576	0	803	1	704	96	71767	768	1	1	71309	25	50760	40584	10121	40100	10000	675169	2707472	1	49	68581	71832	71692	65146	3	65314	50100	40200	10000	70200	10000	71714	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10904	153	541	10661	282	9	884	80	34	10875	128	1	130	0	5	2610	1	51	1	1	71443	40476	852	860	952	10000	40100	71624	71584	71681	71787	71699
50204	71692	535	0	0	0	0	573	0	799	1	688	144	71689	801	2	1	71564	25	50765	40644	10118	40100	10000	676418	2715683	1	49	68635	71618	71719	65088	3	65518	50100	40200	10000	70200	10000	71705	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10857	142	476	10657	250	11	939	50	40	10896	131	1	124	0	3	2610	1	57	1	1	71581	40540	950	982	922	10000	40100	71665	71860	71864	71945	71749

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1880

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72265	540	0	0	402	835	1	640	2	112	71792	793	7	3	71573	25	50700	40546	10136	40010	10000	614191	2728524	1	49	68747	0	71849	71946	65169	3	65684	50010	40020	10000	70020	10000	72053	35	1	1	40021	10	9	10	10000	30010	10000	10	10861	0	152	492	10635	259	13	892	76	1979	10880	120	7	114	0	5	0	0	2520	0	2	85	1	3	71707	40516	971	901	1135	10000	40010	71697	71895	71797	72023	71882
50024	72047	537	0	0	411	811	1	704	0	116	71635	802	8	6	71592	25	50695	40522	10126	40010	10000	611817	2718327	1	49	68705	0	71834	71893	65364	3	65468	50010	40020	10000	70020	10000	71662	35	1	1	40021	10	9	10	10000	30010	10000	10	10919	0	138	486	10629	259	7	892	30	19	10904	134	8	119	3	7	0	0	2520	0	1	85	1	1	71719	40492	992	997	1057	10000	40010	71919	71868	71736	71818	71904
50024	71859	539	0	0	439	817	1	752	0	100	71853	812	6	4	71625	25	50615	40514	10119	40010	10000	612956	2725483	0	49	68795	0	71966	71739	65357	3	65498	50010	40020	10000	70020	10000	71820	35	1	1	40021	10	9	10	10000	30010	10000	10	10870	0	150	481	10657	264	10	920	74	22	10914	119	3	123	0	3	0	0	2520	3	1	85	1	2	71705	40548	1105	996	1129	10000	40010	71788	72012	72062	72019	72066
50024	71978	539	0	0	434	822	1	656	0	136	71923	799	7	5	71684	25	50675	40478	10126	40010	10000	612983	2721147	1	49	68777	0	71939	72014	65343	3	65627	50010	40020	10000	70020	10000	71871	35	1	1	40021	10	9	10	10000	30010	10000	10	10957	0	149	507	10662	269	11	894	78	30	10879	128	7	118	0	3	0	0	2520	3	1	85	1	1	71637	40560	1137	955	1062	10000	40010	71824	72009	71933	71926	71900
50024	71962	538	0	0	376	832	1	712	0	116	71970	803	7	3	71665	25	50680	40538	10125	40010	10000	612984	2726758	0	49	68602	0	71887	71951	65405	3	65420	50010	40020	10000	70020	10000	71733	35	1	1	40021	10	9	10	10000	30010	10000	10	10894	0	164	511	10652	264	6	912	66	16	10930	117	7	107	0	3	0	0	2520	0	3	71	1	1	71864	40548	1029	1028	1126	10000	40010	71832	71982	72002	71919	71978
50024	71852	538	0	0	426	805	1	760	0	120	71987	775	7	5	71448	25	50685	40542	10124	40010	10000	612582	2729698	1	49	68849	0	71922	71931	65207	3	65594	50010	40020	10000	70310	10000	71763	35	1	1	40021	10	9	10	10000	30010	10000	10	10872	0	170	480	10620	259	6	895	50	27	10924	122	6	120	0	3	0	1	2520	0	3	85	1	1	71638	40516	1027	1008	1092	10000	40010	72010	71910	71968	71918	71893
50024	71900	538	0	0	432	873	1	760	0	108	71930	765	6	4	71664	25	50710	40534	10137	40010	10000	611774	2719699	1	49	69047	0	71863	71997	65224	3	65670	50010	40020	10000	70020	10000	71933	35	1	1	40021	10	9	10	10000	30010	10000	10	10905	0	124	503	10622	288	7	949	30	23	10891	130	7	113	0	3	0	0	2520	0	1	85	1	2	71745	40560	956	1078	1034	10000	40010	71855	72005	71810	72001	71887
50024	71992	539	0	0	441	828	1	640	0	100	71870	759	7	4	71783	25	50660	40506	10141	40010	10049	614726	2727214	1	49	68959	0	72130	71879	65302	3	65628	50010	40020	10000	70020	10000	71930	35	1	1	40021	10	9	10	10000	30010	10000	10	10928	0	160	488	10662	266	8	902	78	23	10923	129	5	137	0	3	0	0	2520	0	1	71	1	1	71775	40556	1072	1031	1007	10000	40010	71807	71824	71910	71848	71908
50024	71900	537	0	0	393	808	1	728	1	152	71995	773	8	3	71612	25	50735	40518	10134	40010	10000	612753	2719772	1	49	68778	0	71708	71876	65345	3	65450	50010	40020	10000	70020	10000	71915	35	1	1	40021	10	9	10	10000	30010	10000	10	10882	0	147	474	10667	262	6	957	72	28	10946	120	7	121	0	3	0	0	2520	0	3	85	1	1	71797	40536	1046	1147	948	10000	40010	71796	71766	71915	71995	71930
50024	71996	538	0	0	450	875	1	704	0	116	71982	779	6	3	71774	25	50655	40490	10133	40010	10000	611840	2726774	0	49	68836	0	71982	71658	65276	3	65676	50010	40020	10000	70020	10000	71834	35	1	1	40021	10	9	10	10000	30010	10000	10	10893	0	150	478	10639	268	9	905	72	29	10899	137	7	125	3	3	0	0	2520	0	2	85	1	1	71485	40508	1052	1088	1008	10000	40010	71935	71718	71692	71850	71811

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6, #8]!
  ldrsh w0, [x7, #8]!
  ldrsh w0, [x8, #8]!
  ldrsh w0, [x9, #8]!
  ldrsh w0, [x10, #8]!
  ldrsh w0, [x11, #8]!
  ldrsh w0, [x12, #8]!
  ldrsh w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3643

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29512	220	0	0	0	0	0	0	0	6414	0	794	1	720	125	140	29194	786	358	2009	1981	1852	25	160152	80160	80000	80100	80000	400842	1279212	0	59	49	26179	29143	29199	8960	3	9120	160100	80200	80000	80200	80000	29297	35	1	1	80201	100	99	23	100	80000	100	80000	1	100	80905	0	445	5221	0	84677	721	11	920	80	4710	86501	737	132	4318	4789	0	0	3	5110	2	16	1	1	28959	23	80049	421	428	74	80000	80100	29236	29001	29036	29243	29061
160204	29257	217	0	0	0	0	0	0	0	6113	0	819	1	720	130	96	29243	807	347	1910	2027	1913	25	160139	80167	80000	80100	80000	400802	1275408	0	55	49	26167	29319	29101	9178	3	9202	160100	80200	80000	80200	80000	29101	35	1	1	80201	100	99	19	100	80000	100	80000	0	100	80900	0	407	5388	0	84909	782	13	870	78	4220	85085	793	123	4408	4851	0	3	3	5110	1	16	1	1	29207	40	80383	421	361	63	80000	80100	29229	29228	29058	29150	29500
160204	29241	219	0	0	0	0	0	1	1	6900	0	836	1	696	117	128	28920	803	372	1950	2157	1749	25	160160	80160	80000	80100	80000	400798	1283133	0	57	49	26116	29240	29172	8932	3	8910	160100	80200	80000	80200	80000	29163	35	2	1	80201	100	99	17	100	80000	100	80000	0	100	80891	0	429	5245	0	84960	741	12	901	34	4635	85507	637	129	4382	5216	0	0	3	5110	1	16	1	1	29217	37	80070	466	381	77	80000	80100	29250	29120	29429	29115	29169
160204	29216	218	0	0	0	0	0	0	0	6572	0	794	1	768	95	112	29133	832	392	1998	1907	2070	25	160161	80160	80000	80100	80000	400758	1289580	1	70	49	25803	29307	29306	9023	3	9025	160100	80200	80000	80200	80000	29335	35	1	1	80201	100	99	16	100	80000	100	80000	0	100	80897	0	443	5898	0	84521	809	11	923	78	4976	85734	727	133	4541	5009	0	0	0	5110	1	16	1	1	28896	31	80060	347	326	61	80000	80100	28982	29103	29108	28999	29087
160204	28915	216	0	0	0	0	0	0	0	6304	0	797	1	760	99	104	29182	788	342	1771	2084	2016	25	160168	80148	80000	80100	80000	400764	1287319	0	51	49	25941	29192	29121	9063	3	9047	160100	80200	80000	80200	80000	29014	35	1	1	80201	100	99	11	100	80000	100	80000	0	100	80887	0	427	5764	0	85274	734	8	875	72	5030	86176	759	123	4289	4508	0	0	5	5110	1	16	1	1	28988	26	80057	368	300	64	80000	80100	28953	29332	29090	29209	29167
160204	29171	218	0	0	0	0	0	0	0	6301	0	831	1	712	109	104	29203	805	344	2002	2156	1996	25	160152	80155	80000	80100	80000	400778	1278623	0	49	49	26043	29239	29164	9043	3	9159	160100	80200	80000	80200	80000	29180	35	1	1	80201	100	99	30	100	80000	100	80000	0	100	80868	0	408	5258	0	84494	786	9	922	80	4355	85705	731	132	5226	4320	0	0	3	5110	1	16	1	1	29319	34	80048	396	392	76	80000	80100	29083	29130	29196	29269	29000
160204	29275	218	0	0	0	0	0	0	0	6476	0	793	1	672	121	136	29215	778	339	1914	2218	1976	25	160161	80148	80000	80100	80000	400781	1286966	0	53	49	26147	29331	28972	9009	3	9077	160100	80200	80000	80200	80000	29147	35	1	1	80201	100	99	25	100	80000	100	80000	0	100	80885	0	461	4837	0	84857	755	9	924	34	4752	85272	811	113	4500	5299	0	3	3	5110	1	16	1	1	29067	35	80056	347	357	58	80000	80100	29249	29303	29226	29067	29102
160204	29111	218	0	0	0	0	0	0	0	6532	0	829	1	712	104	128	29057	808	345	1998	1976	1883	25	160154	80161	80000	80100	80000	401562	1281465	0	58	49	25960	29211	29219	9027	3	9287	160100	80200	80000	80200	80000	29303	35	1	1	80201	100	99	21	100	80000	100	80000	0	100	80934	0	428	5112	0	84660	772	10	951	46	4600	86086	699	138	4826	4572	0	0	4	5110	1	16	1	1	28966	22	80042	356	335	70	80000	80100	29204	29155	28975	29127	29133
160204	29179	219	0	0	0	0	0	0	0	5818	0	844	1	672	107	328	29274	822	393	2016	1824	1952	25	160152	80161	80000	80100	80000	400773	1276818	0	66	49	26065	29226	29202	9102	3	9014	160100	80200	80000	80200	80000	28990	35	1	1	80201	100	99	25	100	80000	100	80000	0	100	80873	0	448	5710	0	84900	781	10	882	72	4968	86105	813	123	4771	5204	0	0	3	5110	1	16	1	1	29137	25	80046	437	377	69	80000	80100	29115	29405	29165	29034	29053
160204	29306	218	0	0	0	0	0	0	0	6185	0	827	1	696	120	148	29191	804	307	1957	1998	2007	25	160150	80154	80000	80100	80000	400825	1285822	0	49	49	26008	29244	29059	8850	3	8956	160100	80200	80000	80200	80000	29137	35	1	1	80201	100	99	16	100	80000	100	80000	0	100	80894	0	430	4642	0	84786	763	9	884	48	4569	85581	718	133	4593	4832	0	3	3	5110	1	16	1	1	28985	31	80048	404	380	76	80000	80100	29250	29256	29054	29262	29271

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3666

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29670	222	2	0	0	0	6691	0	838	1	696	86	104	29252	818	350	1912	1953	2034	25	160076	80081	80000	80010	80000	400349	1289593	0	71	49	26217	29133	29242	9310	0	3	9335	160010	80020	80000	80020	80000	29601	35	1	1	80021	10	9	34	10	80000	10	80000	0	10	80872	385	5596	0	84974	664	10	864	58	4813	85916	756	112	5120	5060	0	0	5019	3	16	1	1	29297	27	80058	524	509	97	80000	80010	29431	29414	29491	29262	29170
160024	29291	219	0	0	0	0	6688	0	805	1	664	90	212	29373	767	353	1663	1792	1982	25	160080	80068	80000	80010	80000	400334	1288446	0	69	49	26239	29502	29303	9358	0	3	9417	160010	80020	80000	80020	80000	29315	35	1	1	80021	10	9	23	10	80000	10	80000	0	10	80897	411	4938	0	85415	646	14	872	32	5060	85790	679	116	4629	5038	0	0	5020	1	17	1	1	29129	33	80066	582	580	89	80000	80010	29477	29229	29301	29262	29288
160024	29424	219	0	0	0	0	5881	0	801	1	688	100	156	29111	800	345	1826	1674	2250	25	160071	80074	80000	80010	80000	400308	1291004	0	60	49	26420	29300	29086	9261	0	3	9521	160010	80020	80000	80020	80000	29423	35	1	1	80021	10	9	45	10	80000	10	80000	0	10	80904	383	5403	0	85660	685	13	899	48	4794	85618	779	118	5441	4843	0	0	5019	1	17	1	1	29195	28	80079	519	508	114	80000	80010	29040	29203	29092	29406	29537
160024	29457	219	0	0	0	0	6799	0	840	1	704	114	140	29252	749	329	1620	1827	2096	25	160099	80079	80000	80010	80000	400329	1296965	0	74	49	26281	29144	29318	9180	0	3	9355	160010	80020	80000	80020	80000	29498	35	1	1	80021	10	9	39	10	80000	10	80000	0	10	80904	354	5221	0	85389	636	11	883	132	5306	85413	666	118	5021	4758	0	0	5019	1	16	1	1	29336	31	80058	539	500	104	80000	80010	29306	29340	29275	29308	29471
160024	29357	219	0	0	0	0	6454	0	824	1	496	106	124	29433	808	343	1842	2193	2195	25	160080	80074	80000	80010	80000	400314	1292647	1	72	49	26133	29316	29189	9282	0	3	9317	160010	80020	80000	80020	80000	29259	35	1	1	80021	10	9	42	10	80000	10	80000	0	10	80861	379	5475	0	85254	653	11	890	30	5502	85999	727	119	4746	4847	0	0	5019	1	17	1	1	29103	25	80059	587	608	109	80000	80010	29538	29482	29248	29199	29246
160024	29323	218	0	0	0	0	7084	0	804	1	688	102	276	29406	804	325	1815	1780	2048	25	160054	80061	80000	80010	80000	400346	1299299	1	66	49	26304	29522	29342	9297	0	3	9516	160010	80020	80000	80020	80000	29242	35	1	1	80021	10	9	33	10	80000	10	80000	0	10	80874	388	5678	0	85639	652	13	894	140	4922	85941	818	127	5033	4999	0	5	5019	1	17	1	1	29474	18	80059	503	527	106	80000	80010	29460	29389	29358	29298	29195
160024	29366	220	0	0	0	0	6691	0	794	1	736	87	148	29164	817	312	1602	1775	1980	25	160080	80069	80000	80010	80000	400323	1284855	1	50	49	26544	29373	29204	9372	0	3	9349	160010	80020	80000	80020	80000	29374	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80901	385	5557	0	85523	668	10	874	112	4788	85864	778	129	5220	4938	3	4	5020	1	16	1	1	29381	27	80079	473	491	105	80000	80010	29158	29201	29176	29269	29388
160024	29337	219	0	0	0	0	6829	0	822	1	680	110	292	29382	807	336	1814	1754	2056	25	160068	80085	80000	80010	80000	400354	1288538	0	57	49	26138	29282	29288	9136	0	3	9354	160010	80020	80000	80020	80000	29257	35	1	1	80021	10	9	19	10	80000	10	80000	0	10	80894	393	5380	0	85270	629	12	868	22	4880	85861	755	109	5286	5168	0	3	5020	1	26	1	1	29249	31	80059	543	506	105	80000	80010	29593	29313	29448	29410	29355
160024	29607	220	0	0	0	0	6699	0	847	1	760	106	156	29230	791	322	1865	1595	2014	25	160067	80074	80000	80010	80000	400302	1283802	1	64	49	26402	29420	29416	9216	0	3	9272	160010	80020	80000	80020	80000	29190	35	1	1	80021	10	9	33	10	80000	10	80000	0	10	80877	398	5457	0	85079	677	12	902	74	5225	85848	803	123	5480	4973	3	3	5019	1	17	1	1	29331	41	80060	516	563	103	80000	80010	29284	29321	29308	29452	29417
160024	29314	220	0	0	0	0	5888	0	833	1	704	110	104	29369	798	334	1629	1741	2013	25	160075	80077	80000	80010	80000	400389	1283767	1	73	49	26123	29224	29150	9431	0	3	9387	160010	80020	80000	80020	80000	29399	35	1	1	80021	10	9	33	10	80000	10	80000	0	10	80910	362	5115	0	84588	631	15	950	26	4910	85605	627	120	4871	5283	0	4	5019	1	16	1	1	29193	31	80070	528	529	110	80000	80010	29263	29270	29411	29148	29325

LDRSH (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations