Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
strh w0, [x6, #8]!
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 7 | 0 | 1 | 0 | 14 | 76 | 1 | 8 | 4 | 1025 | 10 | 2 | 3 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 933 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1013 | 0 | 33 | 2 | 14 | 1005 | 0 | 40 | 0 | 13 | 1042 | 5 | 55 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 10 | 6 | 0 | 6 | 12 | 1025 | 11 | 0 | 20 | 4 | 36 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 0 | 28 | 0 | 0 | 1005 | 0 | 0 | 0 | 5 | 1005 | 5 | 39 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 6 | 10 | 44 | 0 | 0 | 0 | 1025 | 15 | 1 | 0 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 6 | 49 | 2 | 9 | 1005 | 0 | 19 | 6 | 5 | 1019 | 10 | 48 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 0 | 12 | 38 | 0 | 10 | 0 | 1025 | 21 | 0 | 7 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1026 | 0 | 58 | 4 | 9 | 1005 | 0 | 10 | 0 | 10 | 1010 | 10 | 32 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 13 | 20 | 1 | 0 | 0 | 1025 | 14 | 4 | 0 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 0 | 60 | 3 | 20 | 1005 | 0 | 14 | 10 | 8 | 1023 | 5 | 24 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 0 | 9 | 20 | 0 | 0 | 0 | 1025 | 0 | 2 | 3 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 897 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 0 | 36 | 0 | 22 | 1014 | 0 | 10 | 6 | 5 | 1014 | 5 | 62 | 73 | 1 | 17 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 0 | 8 | 36 | 1 | 5 | 0 | 1025 | 13 | 2 | 2 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1020 | 0 | 60 | 0 | 28 | 1005 | 0 | 22 | 16 | 8 | 1018 | 5 | 48 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 9 | 26 | 0 | 8 | 0 | 1025 | 11 | 3 | 3 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1020 | 0 | 37 | 2 | 20 | 1005 | 0 | 10 | 0 | 5 | 1025 | 10 | 31 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 1 | 0 | 14 | 20 | 1 | 6 | 0 | 1025 | 15 | 2 | 2 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 12 | 73 | 0 | 0 | 1005 | 0 | 0 | 0 | 10 | 1010 | 10 | 55 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 14 | 38 | 0 | 6 | 4 | 1025 | 0 | 0 | 0 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 0 | 29 | 1 | 17 | 1006 | 0 | 26 | 18 | 5 | 1019 | 10 | 39 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
strh w0, [x6, #8]!
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 18 | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10209 | 10040 | 75 | 0 | 0 | 0 | 2067 | 86 | 770 | 1 | 640 | 87 | 0 | 116 | 10025 | 794 | 51 | 88 | 61 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522119 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10910 | 0 | 1311 | 356 | 0 | 633 | 10259 | 248 | 874 | 32 | 847 | 10924 | 15 | 1107 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 2136 | 76 | 808 | 1 | 680 | 83 | 0 | 116 | 10025 | 801 | 56 | 101 | 60 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522115 | 471113 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10870 | 0 | 1193 | 353 | 2 | 656 | 10236 | 268 | 872 | 36 | 803 | 10902 | 12 | 1092 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 2202 | 85 | 800 | 1 | 728 | 73 | 1 | 108 | 10025 | 748 | 82 | 77 | 118 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522141 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10892 | 0 | 1187 | 350 | 0 | 626 | 10267 | 246 | 856 | 32 | 809 | 10910 | 8 | 1131 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 4 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 2067 | 78 | 805 | 1 | 752 | 88 | 2 | 148 | 10025 | 784 | 54 | 71 | 61 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522079 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10894 | 0 | 1131 | 391 | 0 | 693 | 10241 | 253 | 870 | 32 | 710 | 10897 | 12 | 1053 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 2 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 2190 | 72 | 784 | 1 | 760 | 76 | 0 | 96 | 10077 | 766 | 55 | 70 | 68 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522039 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10908 | 0 | 1160 | 375 | 2 | 655 | 10247 | 267 | 908 | 36 | 822 | 10893 | 9 | 1147 | 7 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 2043 | 88 | 793 | 1 | 688 | 60 | 1 | 120 | 10025 | 767 | 60 | 68 | 53 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522113 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10870 | 0 | 1210 | 348 | 0 | 659 | 10256 | 258 | 900 | 32 | 842 | 10895 | 9 | 1180 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 1962 | 72 | 774 | 1 | 712 | 81 | 0 | 144 | 10025 | 764 | 80 | 39 | 57 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522015 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10908 | 0 | 1290 | 362 | 0 | 679 | 10291 | 278 | 914 | 38 | 851 | 10940 | 12 | 1182 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 1971 | 80 | 787 | 1 | 672 | 68 | 0 | 116 | 10025 | 798 | 82 | 73 | 51 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522057 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10089 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10870 | 0 | 1358 | 354 | 1 | 626 | 10270 | 239 | 896 | 38 | 838 | 10884 | 6 | 1056 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10116 | 10000 | 4 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 1938 | 76 | 802 | 1 | 712 | 81 | 0 | 108 | 10025 | 773 | 86 | 63 | 58 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522109 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10931 | 0 | 1366 | 370 | 0 | 668 | 10262 | 258 | 874 | 58 | 831 | 10878 | 12 | 1184 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 2172 | 75 | 794 | 1 | 720 | 87 | 1 | 116 | 10025 | 785 | 73 | 49 | 51 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522125 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20247 | 200 | 10000 | 200 | 20000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10914 | 0 | 1236 | 357 | 3 | 657 | 10267 | 302 | 862 | 32 | 851 | 10913 | 10 | 1154 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10029 | 10040 | 75 | 1 | 1 | 0 | 2322 | 91 | 826 | 1 | 704 | 82 | 0 | 116 | 10025 | 777 | 108 | 74 | 63 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521009 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10931 | 7 | 1322 | 369 | 0 | 686 | 10297 | 319 | 0 | 936 | 40 | 903 | 10918 | 21 | 1254 | 7 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 2 | 2 | 0 | 2310 | 100 | 800 | 1 | 792 | 68 | 0 | 100 | 10025 | 774 | 120 | 90 | 60 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10901 | 7 | 1366 | 352 | 0 | 664 | 10286 | 272 | 4 | 929 | 44 | 850 | 10918 | 28 | 1236 | 14 | 2 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 2280 | 91 | 812 | 1 | 680 | 89 | 0 | 104 | 10025 | 777 | 84 | 76 | 63 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521009 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10923 | 8 | 1352 | 351 | 0 | 659 | 10298 | 290 | 0 | 886 | 38 | 912 | 10910 | 21 | 1213 | 7 | 2 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 4 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 2220 | 77 | 785 | 1 | 736 | 82 | 0 | 152 | 10025 | 770 | 78 | 111 | 66 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521081 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10080 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10851 | 7 | 1347 | 367 | 0 | 665 | 10271 | 248 | 4 | 903 | 48 | 832 | 10914 | 29 | 1268 | 14 | 2 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 1 | 2058 | 80 | 802 | 1 | 744 | 76 | 0 | 112 | 10025 | 751 | 56 | 57 | 67 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521025 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10887 | 7 | 1376 | 376 | 0 | 670 | 10285 | 252 | 0 | 892 | 50 | 913 | 10879 | 20 | 1305 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 1 | 2091 | 97 | 793 | 1 | 752 | 76 | 0 | 116 | 10025 | 802 | 36 | 91 | 69 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10896 | 16 | 1305 | 353 | 2 | 673 | 10290 | 302 | 1 | 896 | 50 | 872 | 10924 | 21 | 1250 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 5 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 2 | 0 | 2088 | 101 | 837 | 1 | 720 | 79 | 0 | 160 | 10025 | 829 | 103 | 88 | 65 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520993 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10907 | 9 | 1355 | 407 | 0 | 652 | 10284 | 293 | 0 | 898 | 38 | 843 | 10900 | 22 | 1160 | 7 | 0 | 640 | 3 | 16 | 3 | 2 | 10037 | 10000 | 0 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 1 | 1 | 1 | 2370 | 94 | 798 | 1 | 744 | 79 | 0 | 108 | 10025 | 785 | 84 | 101 | 58 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521025 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10879 | 14 | 1258 | 373 | 0 | 665 | 10277 | 281 | 0 | 920 | 50 | 899 | 10918 | 18 | 1238 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 4 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 2118 | 95 | 771 | 1 | 688 | 75 | 0 | 108 | 10025 | 767 | 90 | 84 | 60 | 25 | 20118 | 10039 | 10000 | 10010 | 10000 | 521041 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10920 | 15 | 1321 | 397 | 0 | 671 | 10290 | 275 | 0 | 876 | 46 | 807 | 10928 | 23 | 1138 | 7 | 0 | 640 | 3 | 16 | 3 | 2 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 0 | 2118 | 100 | 815 | 1 | 696 | 88 | 0 | 104 | 10025 | 775 | 97 | 77 | 60 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521065 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10903 | 7 | 1373 | 347 | 0 | 680 | 10287 | 270 | 2 | 905 | 44 | 857 | 10896 | 22 | 1221 | 14 | 2 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 5 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
strh w0, [x6, #8]! strh w0, [x7, #8]! strh w0, [x8, #8]! strh w0, [x9, #8]! strh w0, [x10, #8]! strh w0, [x11, #8]! strh w0, [x12, #8]! strh w0, [x13, #8]!
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5096
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80209 | 40730 | 307 | 3 | 0 | 0 | 0 | 3 | 0 | 0 | 1824 | 856 | 804 | 1 | 720 | 114 | 104 | 40717 | 773 | 1721 | 1828 | 163 | 25 | 160490 | 80540 | 80000 | 80100 | 80000 | 408436 | 1878424 | 1 | 385 | 49 | 37645 | 40730 | 40820 | 30671 | 3 | 30670 | 160100 | 200 | 80000 | 200 | 160000 | 40857 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80875 | 26 | 4017 | 501 | 16 | 870 | 80509 | 259 | 0 | 889 | 72 | 1567 | 81394 | 443 | 4196 | 27 | 0 | 0 | 5110 | 2 | 17 | 2 | 3 | 40858 | 80615 | 80000 | 80100 | 40787 | 40717 | 40770 | 40819 | 40772 |
| 80204 | 40794 | 305 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 1824 | 778 | 805 | 1 | 664 | 105 | 128 | 40803 | 730 | 1603 | 1803 | 191 | 25 | 160566 | 83437 | 80000 | 80100 | 80000 | 417348 | 1876748 | 0 | 388 | 49 | 37662 | 40777 | 40953 | 30791 | 3 | 30831 | 160100 | 200 | 80000 | 200 | 160000 | 40927 | 88 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80984 | 16 | 4131 | 453 | 6 | 889 | 80528 | 249 | 0 | 865 | 34 | 1682 | 81397 | 495 | 4540 | 27 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40739 | 80931 | 80000 | 80100 | 40750 | 40766 | 40712 | 40816 | 40793 |
| 80204 | 40780 | 305 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1695 | 707 | 796 | 1 | 672 | 108 | 92 | 40741 | 782 | 1667 | 1697 | 170 | 25 | 165238 | 86246 | 80000 | 80100 | 80000 | 401451 | 1877084 | 0 | 2029 | 49 | 37674 | 40811 | 40809 | 30708 | 3 | 30695 | 160100 | 200 | 80000 | 200 | 160000 | 40682 | 87 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80892 | 29 | 4245 | 483 | 7 | 872 | 80551 | 263 | 2 | 842 | 36 | 1585 | 81381 | 575 | 4449 | 27 | 0 | 0 | 5110 | 2 | 17 | 2 | 2 | 40802 | 80324 | 80000 | 80100 | 40728 | 40729 | 40840 | 40776 | 40681 |
| 80204 | 40693 | 305 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 1860 | 716 | 786 | 1 | 760 | 116 | 72 | 40729 | 766 | 1675 | 1810 | 176 | 25 | 164625 | 80528 | 80000 | 80100 | 80000 | 411164 | 1867988 | 1 | 1408 | 49 | 37722 | 40769 | 40696 | 30674 | 3 | 30730 | 160100 | 200 | 80000 | 200 | 160000 | 40766 | 84 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80876 | 27 | 4481 | 476 | 19 | 827 | 80477 | 245 | 0 | 881 | 64 | 1479 | 81387 | 488 | 4516 | 20 | 0 | 0 | 5110 | 2 | 17 | 2 | 2 | 40825 | 80621 | 80000 | 80100 | 40716 | 40750 | 40830 | 40777 | 40786 |
| 80204 | 40777 | 306 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1773 | 750 | 879 | 1 | 648 | 86 | 84 | 40708 | 752 | 1801 | 1708 | 174 | 25 | 163170 | 84392 | 80002 | 80100 | 80000 | 402579 | 1867792 | 0 | 1783 | 49 | 37675 | 40735 | 40749 | 30564 | 3 | 30704 | 160100 | 200 | 80000 | 200 | 160000 | 40755 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80929 | 36 | 4481 | 476 | 8 | 856 | 80574 | 235 | 0 | 910 | 32 | 1450 | 81367 | 560 | 4331 | 25 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40760 | 80205 | 80000 | 80100 | 40798 | 40636 | 40747 | 40751 | 40746 |
| 80204 | 40760 | 305 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 1752 | 780 | 769 | 1 | 696 | 114 | 144 | 40718 | 767 | 1616 | 1963 | 173 | 25 | 160718 | 81643 | 80000 | 80100 | 80000 | 401882 | 1874608 | 0 | 249 | 49 | 37656 | 40811 | 40761 | 30672 | 3 | 30718 | 160100 | 200 | 80000 | 200 | 160000 | 40688 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80889 | 24 | 4632 | 523 | 15 | 878 | 80498 | 281 | 0 | 851 | 68 | 1654 | 81396 | 626 | 3938 | 22 | 0 | 0 | 5110 | 2 | 17 | 2 | 2 | 40699 | 80741 | 80000 | 80100 | 40740 | 40683 | 40781 | 40720 | 40696 |
| 80204 | 40833 | 306 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 1755 | 762 | 747 | 1 | 696 | 110 | 112 | 40673 | 769 | 1851 | 1598 | 172 | 25 | 160815 | 80779 | 80000 | 80100 | 80000 | 422783 | 1874444 | 1 | 2069 | 49 | 37607 | 40788 | 40777 | 30688 | 3 | 30708 | 160100 | 200 | 80000 | 200 | 160000 | 40734 | 76 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80876 | 7 | 4340 | 500 | 9 | 849 | 80524 | 258 | 0 | 878 | 32 | 1641 | 81369 | 463 | 3827 | 13 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40816 | 84617 | 80000 | 80100 | 40778 | 40792 | 40791 | 40741 | 40788 |
| 80204 | 40770 | 305 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1719 | 808 | 793 | 1 | 696 | 112 | 128 | 40703 | 780 | 1860 | 1764 | 166 | 25 | 165978 | 85542 | 80000 | 80100 | 80000 | 421077 | 1872716 | 0 | 298 | 49 | 37640 | 40839 | 40796 | 30778 | 3 | 30618 | 160100 | 200 | 80000 | 200 | 160000 | 40757 | 88 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80907 | 25 | 4121 | 481 | 11 | 856 | 80516 | 254 | 0 | 873 | 74 | 1564 | 81351 | 518 | 3643 | 26 | 0 | 0 | 5110 | 2 | 17 | 2 | 2 | 40760 | 85723 | 80000 | 80100 | 40862 | 40781 | 40716 | 40856 | 40724 |
| 80204 | 40697 | 305 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 1872 | 695 | 790 | 1 | 664 | 96 | 120 | 40700 | 763 | 1648 | 1857 | 185 | 25 | 160756 | 80436 | 80000 | 80100 | 80000 | 408888 | 1872760 | 0 | 1865 | 49 | 37722 | 40681 | 40747 | 30749 | 3 | 30747 | 160100 | 200 | 80000 | 200 | 160000 | 40693 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80889 | 28 | 3758 | 467 | 11 | 840 | 80522 | 253 | 0 | 821 | 126 | 1596 | 81365 | 490 | 3778 | 27 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40789 | 80632 | 80000 | 80100 | 40830 | 40741 | 40831 | 40948 | 40647 |
| 80204 | 40646 | 305 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 1929 | 620 | 768 | 1 | 712 | 106 | 144 | 40837 | 759 | 1594 | 1813 | 183 | 25 | 160882 | 81011 | 80000 | 80100 | 80000 | 403024 | 1870436 | 0 | 381 | 49 | 37705 | 40702 | 40727 | 30720 | 3 | 30794 | 160100 | 200 | 80000 | 200 | 160000 | 40760 | 87 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80864 | 28 | 4686 | 632 | 5 | 841 | 80562 | 273 | 1 | 846 | 32 | 1521 | 81386 | 550 | 4264 | 13 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40793 | 80554 | 80000 | 80100 | 40834 | 40746 | 40769 | 40742 | 40854 |
Result (median cycles for code divided by count): 0.5097
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80029 | 40681 | 306 | 0 | 0 | 0 | 1629 | 810 | 807 | 1 | 712 | 126 | 112 | 40804 | 748 | 1853 | 1533 | 129 | 25 | 161477 | 80734 | 80059 | 80010 | 80000 | 401968 | 1879652 | 1 | 2111 | 49 | 37677 | 40740 | 40834 | 30721 | 3 | 30823 | 160010 | 20 | 80000 | 20 | 160000 | 40761 | 92 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80899 | 14 | 3641 | 458 | 12 | 864 | 80570 | 237 | 0 | 869 | 30 | 1679 | 81324 | 578 | 4222 | 14 | 0 | 5020 | 6 | 16 | 6 | 7 | 40870 | 80555 | 80000 | 80010 | 40825 | 40841 | 40921 | 40881 | 40788 |
| 80024 | 40816 | 306 | 0 | 1 | 0 | 1956 | 843 | 768 | 1 | 688 | 111 | 224 | 40870 | 797 | 1486 | 1794 | 120 | 25 | 160566 | 80604 | 80000 | 80010 | 80000 | 401223 | 1875112 | 1 | 910 | 49 | 37636 | 40727 | 40754 | 30751 | 3 | 30740 | 160010 | 20 | 80000 | 20 | 160000 | 40783 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80904 | 0 | 3929 | 502 | 15 | 902 | 80476 | 260 | 0 | 848 | 72 | 1648 | 81413 | 512 | 3969 | 0 | 0 | 5020 | 7 | 16 | 6 | 6 | 40774 | 80972 | 80000 | 80010 | 40777 | 40760 | 40733 | 40830 | 40748 |
| 80024 | 40848 | 306 | 0 | 0 | 0 | 1659 | 757 | 795 | 1 | 696 | 113 | 120 | 40795 | 739 | 1719 | 1661 | 120 | 25 | 162356 | 80732 | 80000 | 80010 | 80000 | 401234 | 1872856 | 1 | 200 | 49 | 37709 | 40768 | 40778 | 30677 | 3 | 30753 | 160010 | 20 | 80000 | 20 | 160000 | 40885 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80874 | 0 | 3916 | 468 | 17 | 830 | 80541 | 249 | 0 | 851 | 42 | 1528 | 81423 | 529 | 3846 | 0 | 0 | 5020 | 6 | 17 | 6 | 4 | 40784 | 80600 | 80000 | 80010 | 40794 | 40794 | 40746 | 40799 | 40756 |
| 80024 | 40768 | 306 | 0 | 0 | 0 | 1641 | 911 | 766 | 1 | 648 | 127 | 108 | 40737 | 744 | 1579 | 1623 | 134 | 25 | 160253 | 85774 | 80000 | 80010 | 80000 | 417624 | 1876912 | 1 | 1582 | 49 | 37660 | 40819 | 40713 | 30690 | 3 | 30653 | 160010 | 20 | 80000 | 20 | 160000 | 40786 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80835 | 0 | 3754 | 462 | 7 | 868 | 80493 | 246 | 0 | 872 | 28 | 1510 | 81306 | 494 | 4065 | 0 | 0 | 5020 | 6 | 17 | 7 | 4 | 40754 | 82757 | 80000 | 80010 | 40710 | 40829 | 40743 | 40738 | 40753 |
| 80024 | 40728 | 305 | 0 | 0 | 0 | 1587 | 678 | 780 | 1 | 680 | 87 | 108 | 40798 | 733 | 1695 | 1480 | 124 | 25 | 163702 | 82150 | 80000 | 80010 | 80000 | 401366 | 1875904 | 1 | 167 | 49 | 37772 | 40809 | 40704 | 30623 | 3 | 30844 | 160010 | 20 | 80000 | 20 | 160000 | 40821 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80861 | 0 | 4028 | 476 | 12 | 893 | 80538 | 238 | 0 | 859 | 34 | 1579 | 81418 | 503 | 3876 | 0 | 0 | 5020 | 7 | 16 | 6 | 4 | 40730 | 80467 | 80000 | 80010 | 40730 | 40839 | 40797 | 40704 | 40802 |
| 80024 | 40830 | 306 | 0 | 0 | 0 | 1830 | 739 | 787 | 1 | 648 | 117 | 100 | 40740 | 775 | 1715 | 1800 | 122 | 25 | 160406 | 82874 | 80000 | 80010 | 80000 | 401389 | 1875256 | 1 | 68 | 49 | 37619 | 40717 | 40822 | 30652 | 3 | 30769 | 160010 | 20 | 80000 | 20 | 160000 | 40724 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80858 | 0 | 3881 | 434 | 9 | 838 | 80465 | 252 | 0 | 832 | 30 | 1575 | 81361 | 536 | 3723 | 0 | 0 | 5020 | 6 | 17 | 6 | 3 | 40785 | 80415 | 80000 | 80010 | 40747 | 40788 | 40836 | 40723 | 40726 |
| 80024 | 40765 | 305 | 1 | 0 | 0 | 1746 | 640 | 748 | 1 | 568 | 106 | 140 | 40704 | 772 | 1884 | 1682 | 137 | 25 | 160256 | 80598 | 80109 | 80010 | 80000 | 401005 | 1872760 | 1 | 299 | 49 | 37736 | 40884 | 40825 | 30726 | 3 | 30717 | 160010 | 20 | 80000 | 20 | 160000 | 40808 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80848 | 0 | 4414 | 471 | 5 | 861 | 80542 | 255 | 0 | 904 | 28 | 1446 | 81410 | 534 | 4164 | 0 | 0 | 5020 | 4 | 17 | 6 | 4 | 40723 | 88463 | 80000 | 80010 | 40755 | 40806 | 40930 | 40849 | 40738 |
| 80025 | 40824 | 305 | 1 | 0 | 0 | 1689 | 815 | 824 | 1 | 656 | 100 | 108 | 40843 | 732 | 1766 | 1519 | 120 | 25 | 160571 | 80682 | 80000 | 80010 | 80000 | 401929 | 1872092 | 1 | 228 | 49 | 37656 | 40800 | 40822 | 30643 | 3 | 30736 | 160010 | 20 | 80000 | 20 | 160000 | 40717 | 91 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80882 | 14 | 4317 | 503 | 7 | 844 | 80536 | 258 | 0 | 872 | 38 | 1514 | 81401 | 531 | 3720 | 14 | 0 | 5020 | 7 | 16 | 7 | 4 | 40700 | 80630 | 80000 | 80010 | 40789 | 40755 | 40768 | 40766 | 40772 |
| 80024 | 40751 | 305 | 1 | 0 | 0 | 1599 | 784 | 782 | 1 | 736 | 112 | 104 | 40786 | 734 | 1705 | 1494 | 98 | 25 | 160658 | 80456 | 80000 | 80010 | 80000 | 401136 | 1874348 | 1 | 355 | 49 | 37667 | 40919 | 40710 | 30713 | 3 | 30724 | 160010 | 20 | 80000 | 20 | 160000 | 40783 | 92 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80860 | 16 | 3575 | 476 | 9 | 848 | 80525 | 263 | 0 | 890 | 32 | 1633 | 81363 | 493 | 3547 | 14 | 0 | 5020 | 7 | 16 | 4 | 6 | 40763 | 80582 | 80000 | 80010 | 40705 | 40776 | 40716 | 40816 | 40714 |
| 80024 | 40700 | 305 | 1 | 0 | 0 | 1776 | 768 | 762 | 1 | 664 | 105 | 116 | 40731 | 764 | 1563 | 1666 | 123 | 25 | 160627 | 80415 | 80000 | 80010 | 80000 | 420428 | 1874091 | 1 | 244 | 49 | 37623 | 40748 | 40725 | 30714 | 3 | 30688 | 160010 | 20 | 80000 | 20 | 160000 | 40713 | 82 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80865 | 0 | 3680 | 485 | 8 | 852 | 80537 | 266 | 0 | 873 | 106 | 1555 | 81402 | 508 | 3923 | 0 | 0 | 5020 | 4 | 16 | 4 | 6 | 40774 | 87473 | 80000 | 80010 | 40742 | 40838 | 40699 | 40762 | 40785 |