Firestorm: SXTH (32-bit) measurements

Code:

  sxth w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	4	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	1	18	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  sxth w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	15	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	201	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	76	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	82	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10081	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	2	0	0	640	2	41	2	2	9940	10047	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	170	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	1	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	82	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	12	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: throughput

Count: 8

Code:

  sxth w0, w8
  sxth w1, w8
  sxth w2, w8
  sxth w3, w8
  sxth w4, w8
  sxth w5, w8
  sxth w6, w8
  sxth w7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13414	100	0	28	27	80136	80136	80148	400710	1	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	1	1	1	5119	1	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	1	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	1	1	1	5119	0	92	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	1	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	1	1	1	5119	0	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	1	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	1	1	1	5119	0	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13401	100	0	729	34	80133	80133	80145	400695	1	49	10322	13401	13401	3323	9	3333	80145	80262	80262	13401	39	1	1	80201	100	99	100	80100	100	2	2	2	5129	1	25	1	1	13399	80033	80100	13402	13402	13403	13403	13403
80204	13401	100	0	64	33	80133	80133	80145	400695	0	49	10322	13402	13401	3323	10	3333	80145	80262	80262	13401	39	1	1	80201	100	99	100	80100	100	2	2	2	5129	1	25	1	1	13398	80033	80100	13402	13402	13402	13402	13402
80204	13401	100	0	64	33	80133	80133	80145	400695	0	49	10321	13402	13401	3323	10	3333	80145	80262	80262	13401	39	1	1	80201	100	99	100	80100	100	2	2	2	5129	1	25	1	1	13398	80033	80100	13403	13403	13403	13402	13402
80204	13401	100	0	64	34	80133	80133	80145	400695	1	49	10321	13402	13401	3323	9	3333	80145	80262	80262	13401	39	1	1	80201	100	99	100	80100	100	2	2	2	5130	1	25	1	1	13399	80033	80100	13402	13402	13402	13403	13402
80204	13401	100	0	64	33	80133	80133	80145	400695	1	49	10321	13401	13402	3323	9	3333	80145	80262	80262	13402	39	1	1	80201	100	99	100	80100	100	2	2	2	5130	1	25	1	1	13398	80033	80100	13402	13402	13403	13402	13402
80204	13401	101	15	64	33	80133	80133	80145	400695	1	49	10321	13401	13401	3323	9	3333	80145	80262	80262	13402	39	1	1	80201	100	99	100	80100	100	2	2	2	5130	1	25	1	1	13398	80033	80100	13402	13403	16028	13402	13402

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	13376	100	0	0	0	621	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5023	10	19	8	18	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	101	0	0	0	77	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5024	12	19	8	19	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	535	25	80010	80010	80010	400050	0	49	10457	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	9	5023	12	19	12	15	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	521	25	80141	80010	80010	400050	1	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5023	8	19	8	18	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	522	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5023	12	19	12	14	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	519	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5022	12	19	13	15	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	511	25	80010	80010	80010	400050	1	49	10291	13371	13371	3330	3	3368	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5022	12	19	8	10	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	383	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5023	12	19	8	10	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	564	25	80010	80010	80010	400050	1	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5022	12	19	12	15	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	123	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5024	8	19	8	10	13368	80000	80010	13372	13372	13372	13372	13372

SXTH (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations