Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (register, 64-bit)

Test 1: uops

Code:

  sub x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410358618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410357618622510001000100016916010351035731386810001000200010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410357618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410358618624710001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410357618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  sub x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357510398772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035756198772510100101001010088664049695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
10204100357547998772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000371013711994110000101001003610036100361003610036
10204100357559898772510100101001010088664049695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035751499877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100015071013711994110000101001003610036100361003610036
10204100357538398772510100101001010088664049695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035756198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035756198772510100101001010088664149695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035756198772510100101001010088664049695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035756198772510100101001010088664049695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575061986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010040064034122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010102200064024122994010000100101003610036100361003610036
1002410035759441986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887840496955100351003586023874010010100202002010035411110021109101001010103064024122994010000100101003610036100361003610036
1002410035752761986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003576061986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
1002410035751861986325100101001010010887841496955100351003586023874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  sub x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575003126198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100007100013711994110000101001003610036100361003610036
1020410035750006198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100007100013711994110000101001003610036100361003610036
1020410035750006198772510100101001010088664104969551003510035858038722101001020020200100354111102011009910010100100137100013711994110000101001003610036100361003610036
1020410035750006198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100037100013711994110000101001003610036100361003610036
10204100357500017298772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100007100013711994110000101001003610036100361003610036
1020410035750106198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100507100013711994110000101001003610036100361003610036
1020410035750006198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100237100013711994110000101001003610036100361003610036
1020410035760006198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100307100013711994110000101001003610036100361003610036
1020410035750006198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100007100013711994110000101001003610036100361003610036
1020410035750006198772510100101001010088664004969551003510035858038722101001020020200100354111102011009910010100100007100013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575061986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010101064024122994010000100101003610036100361003610036
100241003575086986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100364024122994010000100101003610036100361003610036
100241003575661986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784496955100351003586023874010010100202002010035411110021109101001010151864024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002020020100354111100211091010010100364024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844964751003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  sub x0, x8, x9
  sub x1, x8, x9
  sub x2, x8, x9
  sub x3, x8, x9
  sub x4, x8, x9
  sub x5, x8, x9
  sub x6, x8, x9
  sub x7, x8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413418100027025801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110319111338380000801001338713387133871338713387
802041338610003525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010015110119111338380000801001338713387133871338713387
802041338610003525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
802041338610003525801008010080100400500049103061338613386394233341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
802041338610009825801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
8020413386101061425801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
8020413386100012325801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
802041338610003525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
8020413386100183525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387
802041338610003525801008010080100400500149103061338613386332333341801008020016020013386391180201100991008010010005110119111338380000801001338713387133871338713387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002413387100000352580010800108001040005000549102911337113371333033348800108002016002013371391180021109108001010515502103380441336880000800101337213372133721337213372
8002413371100000605258001080010801444000500004910291133711337133303334880010800201600201337139118002110910800101006502004190421336880000800101337213372133721337213372
8002413371100000352580010800108001040005000049102911337113371333033348800108002016002013371391180021109108001010112502104190531336880000800101337213372133721337213372
800241337110000035258001080010800104000500004910291133711337133303334880010800201600201337139118002110910800101000502104190441336880000800101337213372133721337213372
800241337110000035258001080010800104000500004910291133711337133303334880010800201600201337139118002110910800101003502104190451336880000800101337213372133721337213372
800241337110000035258001080010800104000500004910291133711337133313334880403800201600201361439118002110910800101000502104192441336880000800101337213372133721337213372
800241337110000035258001080010800104039600004910291133711337133303334880010800201600201337139118002110910800101000502103190461336880000800101337213372133721337213372
8002413371100000568258001080010800104000500004910291133711337133303334880010800201600201337139118002110910800101006502105190551336880000800101337213372133721337213372
800241337110000035258001080010800104093941154910291133711337133303334880010800201600201337139118002110910800101000502102190341336880000800101337213372133721337213372
800241337110000035258001080010800104000500004910291133711337133303334880010800201600201339139118002110910800101000502103190331336880000800101337213372133721337213372