Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (register, lsl, 64-bit)

Test 1: uops

Code:

  cmp x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
1004709606110003042520002000100040877170970949821356110001000200070978111001100000073222116842000710710710710710
1004709506110003042520002000100040877170970949825356110001000200070978111001100000073122116842000710710710710710
1004709506110003042520002000100040877170970949825356110001000200070978111001100000073122116842000710710710710710
1004709506110003042520002000100040877170970949821356110001000200070978111001100000073122116842000710710710710710
1004709506110003042520002000100040877170970949821356110001000200070978111001100000073122116842000710710710710710
1004709506110003042520002000100040877170970949821356110001000200070978111001100000073122116842000710710710710710
1004709506110003042520002000100040877170970949821356110001000200070978111001100000073122116842000710710710710710
1004709506110003042520002000100040877170970949825356110001000200070978111001100000073122116842000710710710710710
10047096061100030425200020001000408771709709498213561100010002000709781110011000015073122116842000710710710710710
1004709536110003042520002000100040877170970949825356110001000200070978111001100000073122116842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp x0, x1, lsl #17
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522400103100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101331222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630081300823008230036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
202043003522500216100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
202043003522500103100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
202043003522500193100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352240061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100210013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433442995830000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433452995830000100103003630036300363003630036
20024300352240009121000029891253001030010200101956289049269553003530035273913274982001020380300203003514511200211091020010100100001270533552999130000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433442995830000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433452995830000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433452995830000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270533452995830000100103003630036300363003630036
200243003522500067941000029891253001030010200101956289049269553003530035273913274982001020377300203003514511200211091020010100100001270433342995830000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270333552995830000100103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433542995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp x0, x1, lsl #17
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250254100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013100231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013100231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101231222995430000101003008130036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101231222995430000101003003630036300363003630036
2020430035225017010000298932530100301002010019561984926955300353003527369327478201792020030200300351451120201100991002010010100015013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101331222995430000101003003630036300363003630036
2020430035224061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101231222995430000101003003630036300363003630036
2020430035224061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101231222995430000101003003630036300363003630036
2020430035224061100002989325301003010020100195619849269553003530035273693274782010020200302003003514511202011009910020100101000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035224061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522552561100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955302163003527391327498200102002030020300351451120021109102001010010001270333112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628904926955300353008027391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
20024300352253061100002989125300103001020010195628904926955300353003527424327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  cmp x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020453456400000618000048741251601001601008010034400051495033053410534104336220603433608010080200160200534107811802011009910080100100000511032411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820503433608010080200160200534107811802011009910080100100100511012411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820603433608010080200160200534107811802011009910080100100000511012411533921600001005345953411534115341153411
8020453410400000618000048741251601001601008010034400051495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
80204534104000007268000048741251601001601008010034400051495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk instruction (07)091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002453402400000618000045278251600121600128001034381300495030053380533804329125573433538001280020160020533807811800211091080010100000502022401153359160000105338153381533815338153381
8002453380400000618000047946251600101600108001034381300495030053380533804329025623433528001080020160020533807811800211091080010100000502012401153359160000105338153381533815338153381
80024533804000012618000047946251600101600108001034381580495030053380533804329027073433528001280020160020533808211800211091080010100000502012401153359160000105338153381533815338153381
8002453380400000618000047946251600101600108001034381300495030053380533804329027073433528001080020160020533807811800211091080010100000502042401153359160000105338153381533815338153381
8002453380400000618000047946251600101600108001034381301495030053380533804329025623433528001080020160020533807811800211091080010100000502012401153359160000105338153381533815338153381
8002453380400100618000047946251600101600108001034381300495030053380533804329025623433528001080020160020533807811800211091080010100000502012401153359160000105338153381533815338153381
8002453380400000618000047946251600101600108001034406391495030053380533804329025623433528001080020160020533807811800211091080010100000502012401153359160002105338153381533815338153381
80024533803990005368000047946251600101600108001034381300495030053380533804329027073433538001080020160020533807811800211091080010100000502012401153359160000105338153381533815338153381
8002453380400000618000047946251600101600108001034381301495030053380533804329027073433528001080020160020533807811800211091080010100000502012401153359160000105338153381533815338153381
80024533804000007268000047946251600101600108001034381301495030053380533804329025623433528001080020160020533807811800211091080010100000502012401153359160000105338153381533815338153381