Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MVN (register, ror, 64-bit)

Test 1: uops

Code:

  mvn x0, x0, ror #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203515013110001735252000200010003257020352035157531842100010001000203542111001100000732671117812000100020362036203620362036
1004203515315610001735252000200010003257020352035157531842100010001000203542111001100000731671117812000100020362036203620362036
1004203515061100017352520002000100032570203520351575318421000100010002035421110011000018731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010001000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010001000203542111001100080731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010001000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010001000203542111001100040731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010001000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010001000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010001000203542111001100010731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  mvn x0, x0, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500126110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150024049210000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534204916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515002946110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150096110000198032520100201001010018534214916955020035200351842931870010100102001020020035421110201100991001010010000710259221979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515000002700611000019743252001020010104501853101491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100201002020035421110021109101001010000010300640263221979220000100102003620036200362003620172
100242003515000001200611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
100242003515000000880611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000300611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010040000000640263221979220000100102003620036200362003620036
100242003515001000001561000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000014000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853100491695520035200351845131871810010100201002020035421110021109101001010000000000640263221979220000100102003620036200362003620036

Test 3: throughput

Count: 8

Code:

  mvn x0, x8, ror #17
  mvn x1, x8, ror #17
  mvn x2, x8, ror #17
  mvn x3, x8, ror #17
  mvn x4, x8, ror #17
  mvn x5, x8, ror #17
  mvn x6, x8, ror #17
  mvn x7, x8, ror #17
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042673224700000028800312614628160182160182802621619060492365226732267321665181666180262803768037626732391180201100991008010010000000011151292160026729160082801002673226733267332673326733
802042673223200000028800312614628160182160182806791619060492365226732267321665181666180262803768037626731391180201100991008010010000000011151290160026729160082801002673326733267332685326733
8020426732232000066028800312614628160182160182802621619060492365226732267321665181666180262803768037626732391180201100991008010010000000011151290160026729160082801002673326733267332673326733
8020426732231000000693800312614628160182160182802621619060492365226732267321665181666180262803768037626732391180201100991008010010000000011151290160026728160082801002673326733267332673326733
80204267312310000207028800312614628160182160182802621619060492365226732267321665181666180262803768037626732391180201100991008010010000000011151290160026729160082801002673326733267332673326733
8020426732214000012070800312614627160182160182802621656280492365226732267321665181666180262803768037626732391180201100991008010010000000011151280160026729160082801002673326733267332673326733
80204267322150000120598800312614628160182160182802621619060492365126732267321665181666180262803768037626732391180201100991008010010000000311151290160026729160082801002673326733267332673326733
8020426732215000012028800312614628160182160182802621619061492365226732267321665181673180262803768037626732391180201100991008010010000000011151290160026729160082801002673326733267332673326733
802042673221500000028800312614628160182160182802621619061492365226732267321665181666180262803768037626732391180201100991008010010000000011151290160026729160082801002673326733267332673326733
802042673220800000028800312614628160182160182802621619060492365226732267321665181666180262803768037626732391180201100991008010010000000011151290160026729160082801002673326733267332673326733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267342000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010406050206224426704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010460050204224426704160000800102671226712267122671226712
800242671120000618000021280251600101601898021816314204923631267112671116623316685800108002080020267113911800211091080010101780502042251026704160000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142049236312671126711166233166858001080020800202671139118002110910800101000050203223426704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010363050203224426704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010343050204224326704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010383050204224426704160000800102671226712267122671226712
80024268272000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010453050205224526704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010193050204224526704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631421492363126711267111662331668580010800208002026711391180021109108001010353050204224526704160000800102671226712267122671226712