Firestorm: BFC (32-bit) measurements

Code:

  bfc w0, #3, #7

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	7	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	3	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	7	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1083	7	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	0	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	1000	1036	164	1	1	1001	1000	0	0	0	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037

Test 2: Latency 1->1

Code:

  bfc w0, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10036	75	0	0	246	25	10100	10100	10100	60499	0	49	6956	10036	10036	8721	7	8740	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	73	25	10100	10100	10100	60499	0	49	6956	10036	10036	8721	6	8739	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	36	25	10100	10100	10100	60499	0	49	6956	10036	10036	8721	6	8740	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	31	0	1	1	1	717	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	329	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	0	16	0	0	10033	10045	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	256	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	19	0	1	1	1	717	0	16	0	0	10070	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8739	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	76	0	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	10208	10036	162	1	1	10201	100	99	100	10100	100	0	3	1	1	1	717	0	16	0	0	10033	10000	10100	10037	10037	10037	10037	10037

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	75	0	201	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	141	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	1	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	89	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	906	25	10032	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	216	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	335	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	318	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	76	0	303	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	24	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	10020	10036	164	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037

Test 3: throughput

Count: 8

Code:

  bfc w0, #3, #7
  bfc w1, #3, #7
  bfc w2, #3, #7
  bfc w3, #3, #7
  bfc w4, #3, #7
  bfc w5, #3, #7
  bfc w6, #3, #7
  bfc w7, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80035	599	0	0	0	46	25	80100	80100	80100	400500	1	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	46	25	80100	80100	80100	400500	1	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5130	2	16	2	2	80031	80045	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	1653	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80367	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	20	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80034	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	62	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	21	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	8	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	311	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	80200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	599	0	0	0	0	0	231	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80071
80024	80035	599	0	0	0	0	0	27	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	1	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	15	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	45	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	5	1	1	80032	80000	0	80010	80036	80036	80036	80036	80073
80024	80035	599	0	0	0	0	0	549	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	36	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	39	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	24	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	33	0	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	72	352	46	25	80010	80010	80010	400050	49	76955	80035	80035	69986	3	70015	80010	80020	80020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	1	16	0	1	1	80032	80000	0	80010	80036	80036	80036	80036	80036

BFC (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations