Firestorm: B.cc (not taken) measurements

Code:

  b.eq .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch cond (94)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3690	5	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	58	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	1	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	1000	1000	0	0	73	1	21	1	1	532	536	536	536	536	536

Count: 8

Code:

  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5017

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	40462	302	0	0	0	28	61	31	80112	80112	80153	1652800	1	0	49	37064	40144	40144	13386	11	13396	80153	80263	80263	40144	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	1	1	1	5124	5	1	0	16	0	0	40141	100	40145	40145	40145	40145	40145
80204	40144	301	0	0	0	28	61	31	80112	80112	80153	1652800	1	0	49	37064	40144	40144	13386	11	13396	80153	80263	80263	40144	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	1	1	1	5124	5	1	0	16	0	0	40141	100	40145	40145	40145	40145	40145
80204	40144	301	0	0	0	28	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5110	0	0	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	301	0	0	0	625	60	25	80100	80100	80100	1652000	0	5	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5110	0	0	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	300	1	0	0	55	60	25	80100	80100	80100	1652000	1	0	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	1	0	0	0	0	0	5110	0	0	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	301	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5110	5	1	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	301	0	0	0	55	60	25	80100	80100	80100	1652000	1	0	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5110	0	0	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	301	0	0	0	55	60	25	80100	80100	80100	1652000	0	5	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5110	5	1	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	300	0	0	0	55	60	25	80100	80100	80100	1652000	0	5	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5110	0	0	2	20	2	2	40132	100	40136	40136	40136	40136	40136
80204	40135	301	0	0	0	55	60	25	80100	80100	80100	1652000	1	5	49	37055	40135	40135	13376	3	13414	80100	80200	80200	40135	32070	1	1	80201	80100	99	80100	100	80100	0	0	0	0	0	0	5511	5	1	112	20	2	2	40132	100	40136	40136	40136	40136	40136

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80024	43567	311	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	5	20	4	4	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	225	5020	0	3	20	165	20	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	3	20	4	4	40042	10	40046	40046	40046	40046	40046
80024	40045	299	0	0	40	25	80010	80010	80010	584075	0	49	36965	40135	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	5	20	5	4	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	40	25	80010	80010	80010	584075	1	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	778	5020	0	4	20	4	3	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	40	25	80010	80010	80010	584075	1	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	4	20	4	3	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	922	25	80010	80010	80010	584075	1	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	3	20	3	5	40042	10	40046	40046	40046	40046	40046
80024	40045	299	0	0	40	25	80010	80010	80010	584075	0	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	3	20	4	4	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	61	25	80010	80010	80010	584075	0	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	1	0	0	0	5020	3	4	20	4	3	40042	10	40046	40046	40046	40046	40046
80024	40045	300	0	0	325	25	80010	80010	80010	584075	0	49	36965	40045	40045	13331	3	13354	80010	80020	80020	40045	40045	1	1	80021	80010	9	80010	10	80010	0	0	0	0	0	5020	0	4	20	3	4	40042	10	40046	40046	40046	40046	40046

B.cc (not taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations