Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
nop
(no loop instructions)
Retires: 1.000
Issues: 0.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | 60 | 6d | 6e | map rewind (75) | map stall (76) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | f5 | f6 | f7 | f8 | fd |
1004 | 153 | 1 | 0 | 28 | 150 | 0 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 3 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 0 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 0 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 0 | 75 | 2 | 16 | 2 | 2 | 150 | 154 | 154 | 154 | 154 | 154 |
Count: 8
Code:
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.1258
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | 1e | 1f | 3a | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80204 | 10087 | 75 | 1 | 0 | 75 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 3 | 16 | 4 | 4 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 75 | 1 | 1 | 24 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 1 | 12 | 5115 | 4 | 16 | 4 | 4 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 75 | 1 | 1 | 0 | 0 | 1 | 42 | 9554 | 100 | 120 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 4 | 16 | 4 | 3 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 75 | 1 | 1 | 0 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5114 | 4 | 16 | 4 | 4 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 75 | 1 | 1 | 0 | 0 | 1 | 517 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 3 | 16 | 4 | 3 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 76 | 1 | 1 | 9 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 4 | 16 | 4 | 3 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 76 | 1 | 1 | 6 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 4 | 16 | 4 | 4 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 75 | 1 | 1 | 12 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 4 | 16 | 4 | 5 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 75 | 1 | 1 | 6 | 0 | 1 | 42 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5114 | 3 | 16 | 3 | 4 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
80204 | 10060 | 76 | 1 | 1 | 0 | 0 | 1 | 63 | 9554 | 100 | 100 | 100 | 500 | 1 | 49 | 6980 | 10060 | 10060 | 3 | 18 | 100 | 200 | 200 | 10060 | 8035 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 100 | 0 | 0 | 5115 | 4 | 16 | 3 | 4 | 10057 | 100 | 10061 | 10061 | 10061 | 10061 | 10061 |
Result (median cycles for code divided by count): 0.1255
retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | a9 | ac | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80024 | 10053 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 1 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 6 | 16 | 4 | 2 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 0 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 2 | 16 | 2 | 4 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 1 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 2 | 16 | 4 | 4 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 0 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5022 | 4 | 16 | 4 | 3 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 1 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 2 | 16 | 4 | 4 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 0 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 4 | 16 | 2 | 4 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 0 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 2 | 16 | 4 | 4 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 0 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5022 | 4 | 16 | 4 | 2 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 1 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10044 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 2 | 16 | 2 | 4 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |
80024 | 10038 | 75 | 0 | 35 | 9982 | 10 | 10 | 10 | 50 | 0 | 49 | 6958 | 10038 | 10038 | 3 | 18 | 10 | 20 | 20 | 10038 | 10038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 5024 | 4 | 16 | 4 | 2 | 10035 | 10 | 10039 | 10039 | 10039 | 10039 | 10039 |