Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NOP

Test 1: uops

Code:

  nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51606d6emap rewind (75)map stall (76)8283flush restart other nonspec (84)85inst all (8c)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0f5f6f7f8fd
100415310281500153153310153153111001007531622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281500153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154
100415310281501153153310153153111001007521622150154154154154154

Test 2: throughput

Count: 8

Code:

  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1258

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
8020410087751075014295541001001005001496980100601006031810020020010060803511802011009910010010000511531644100571001006110061100611006110061
80204100607511240142955410010010050014969801006010060318100200200100608035118020110099100100100112511541644100571001006110061100611006110061
802041006075110014295541001201005001496980100601006031810020020010060803511802011009910010010000511541643100571001006110061100611006110061
802041006075110014295541001001005001496980100601006031810020020010060803511802011009910010010000511441644100571001006110061100611006110061
8020410060751100151795541001001005001496980100601006031810020020010060803511802011009910010010000511531643100571001006110061100611006110061
802041006076119014295541001001005001496980100601006031810020020010060803511802011009910010010000511541643100571001006110061100611006110061
802041006076116014295541001001005001496980100601006031810020020010060803511802011009910010010000511541644100571001006110061100611006110061
8020410060751112014295541001001005001496980100601006031810020020010060803511802011009910010010000511541645100571001006110061100611006110061
802041006075116014295541001001005001496980100601006031810020020010060803511802011009910010010000511431634100571001006110061100611006110061
802041006076110016395541001001005001496980100601006031810020020010060803511802011009910010010000511541634100571001006110061100611006110061

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1255

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
80024100537503599821010105014969581003810038318102020100381003811800211091010100000050246164210035101003910039100391003910039
80024100387503599821010105004969581003810038318102020100381003811800211091010100000050242162410035101003910039100391003910039
80024100387503599821010105014969581003810038318102020100381003811800211091010100000050242164410035101003910039100391003910039
80024100387503599821010105004969581003810038318102020100381003811800211091010100000050224164310035101003910039100391003910039
80024100387503599821010105014969581003810038318102020100381003811800211091010100000050242164410035101003910039100391003910039
80024100387503599821010105004969581003810038318102020100381003811800211091010100000050244162410035101003910039100391003910039
80024100387503599821010105004969581003810038318102020100381003811800211091010100000050242164410035101003910039100391003910039
80024100387503599821010105004969581003810038318102020100381003811800211091010100000050224164210035101003910039100391003910039
80024100387503599821010105014969581003810038318102020100441003811800211091010100000050242162410035101003910039100391003910039
80024100387503599821010105004969581003810038318102020100381003811800211091010100000050244164210035101003910039100391003910039