Firestorm: STLRH measurements

Code:

  stlrh w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	1088	8	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	1	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	3	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	1	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	2	1000	0	9	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	0	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	7	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	9	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	1	1	1065	16	25	1000	1000	1000	45152	1	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	0	1000	0	0	0	1000	60	73	1	16	1	1	1077	15	15	11	1000	1081	1081	1081	1081	1081

Count: 8

Code:

  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0010

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	80080	599	0	0	0	0	0	0	0	1	0	0	80065	16	25	80100	100	80000	100	80000	500	3758152	49	76967	80028	80080	69911	3	70038	80100	200	80000	200	160000	80080	63918	1	1	80201	100	99	100	80000	100	80000	100	80000	60	0	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80048	80081	80081	80081	80081
80204	80080	600	0	0	0	0	0	0	1	1	0	0	80065	16	25	80100	100	80000	100	80000	500	3758152	49	76967	80028	80080	69911	3	70038	80100	200	80000	200	160000	80080	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80044	0	15	0	11	80000	100	80081	80081	80081	80081	80081
80204	80080	599	0	0	0	0	0	0	1	0	0	0	80065	16	25	80100	100	80000	100	80000	500	3758152	49	77000	80028	80080	69911	3	70038	80100	200	80000	200	160000	80080	63918	1	1	80201	100	99	100	80000	100	80000	100	80000	60	0	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80048	80081	80081	80081	80081
80204	80080	599	0	0	0	0	0	0	1	0	0	0	80065	0	25	80100	100	80000	100	80000	500	3758152	49	77000	80028	80047	69911	3	70038	80100	200	80000	200	160000	80080	63918	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	21	80060	60	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80081	80081	80081	80081	80081
80204	80080	599	0	0	0	0	0	0	1	1	0	0	80065	16	25	80100	100	80000	100	80000	500	3758152	49	77000	79995	80080	69911	3	70005	80100	200	80000	200	160000	80047	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	0	80000	0	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80081	80048	80081	80048	80081
80204	80047	600	0	0	0	0	0	0	0	1	0	0	80065	16	25	80100	100	80000	100	80000	500	3758152	49	77000	80028	80080	69878	3	70038	80100	200	80000	200	160000	80080	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80081	80048	80081	80081	80081
80204	80080	600	0	0	0	0	0	0	0	1	0	0	80065	16	25	80100	100	80000	100	80000	500	3760036	49	77000	80028	80080	69911	3	70038	80100	200	80000	200	160000	80080	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80077	0	0	15	0	80000	100	80081	80048	80081	80081	80081
80204	80080	599	0	0	0	0	0	0	1	1	0	0	80032	16	25	80100	100	80000	100	80000	500	3758152	49	77000	80028	80080	69911	3	70038	80100	200	80000	200	160000	80047	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80081	80081	80081	80081	80081
80204	80080	600	0	0	0	0	0	0	0	0	0	0	80032	0	25	80100	100	80000	100	80000	500	3758152	49	77000	80028	80047	69911	3	70005	80100	200	80000	200	160000	80047	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	60	10	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80077	0	15	15	11	80000	100	80048	80081	80081	80081	80081
80204	80080	600	0	0	0	0	0	0	1	1	0	0	80065	16	25	80100	100	80000	107	80000	500	3756568	49	77000	79995	80080	69911	3	70005	80100	200	80000	200	160000	80080	63951	1	1	80201	100	99	100	80000	100	80000	100	80000	0	10	0	80000	0	0	0	80000	60	0	0	0	5110	1	16	1	1	80044	0	15	15	0	80000	100	80081	80081	80081	80048	80081

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0010

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	80084	600	0	0	0	0	0	1	0	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	77004	80032	80084	69937	3	70027	80010	20	80000	20	160000	80084	80047	1	1	80021	10	9	10	80000	10	80000	10	80000	0	14	0	80000	0	0	0	80000	60	0	5020	0	4	16	8	2	2	80081	0	19	19	0	80000	10	80085	80085	80085	80085	80085
80024	80084	600	0	0	0	0	0	1	0	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	77004	79995	80047	69937	3	70064	80010	20	80000	20	160000	80047	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	60	14	0	80000	0	0	0	80000	60	0	5020	0	2	16	5	2	3	80044	0	0	19	15	80000	10	80085	80085	80048	80085	80048
80024	80047	599	0	0	0	0	0	1	1	0	0	80032	20	25	80010	10	80000	10	80000	50	3758344	1	49	77078	79995	80086	69937	16	70193	80010	20	80000	20	160000	80084	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	60	14	0	80000	0	0	0	80000	60	0	5020	0	2	16	5	3	2	80081	0	0	0	15	80000	10	80048	80085	80085	80085	80085
80024	80084	600	0	0	0	0	0	1	0	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	76967	79995	80084	69937	3	70064	80010	20	80000	20	160000	80084	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	0	14	0	80000	0	0	0	80000	0	0	5046	0	2	16	6	3	3	80081	0	19	19	15	80000	10	80085	80085	80085	80048	80085
80024	80084	600	0	0	0	0	0	1	0	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	77004	79995	80084	69937	3	70064	80010	20	80000	20	160000	80047	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	60	14	0	80000	0	0	3	80000	0	0	5038	0	2	16	5	4	2	80081	0	19	19	15	80000	10	80048	80085	80085	80085	80085
80024	80084	600	0	0	0	0	0	0	0	0	0	80069	0	25	80010	10	80000	10	80000	50	3756568	0	49	77004	79995	80084	69937	3	70064	80010	20	80000	20	160000	80047	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	80000	0	0	0	80000	0	0	5020	0	2	16	5	3	3	80081	0	19	19	0	80000	10	80048	80085	80048	80085	80085
80024	80084	600	0	0	0	0	0	1	0	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	0	49	77004	80032	80084	69937	3	70064	80010	20	80000	20	160000	80084	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	60	14	0	80000	0	0	0	80000	60	0	5020	0	2	16	5	2	2	80081	0	19	19	15	80000	10	80085	80048	80085	80085	80048
80024	81829	613	1	1	28	28	3828	2553	1	0	0	82115	1891	925	80010	10	80000	10	80000	50	3756568	0	49	77004	80032	80084	69937	3	70064	80010	20	80121	20	160000	80084	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	0	31	0	80000	0	0	0	80000	0	0	5020	0	2	16	5	2	2	80081	0	19	19	15	80000	10	80085	80085	80085	80085	80048
80024	80084	600	0	0	0	0	0	1	0	0	0	80069	20	25	80010	10	80000	10	80000	50	3758344	1	49	77004	80032	80084	69937	3	70064	80010	20	80726	20	164840	80084	81367	24	1	80021	10	9	10	80000	10	80000	10	81924	60	524	3	81800	1	4	30765	81740	60	0	5020	0	2	24	5	3	4	81001	0	19	0	15	80000	10	81339	81434	81207	81400	81169
80024	81470	610	0	0	0	0	144	89	0	0	0	80069	569	595	81271	13	81200	10	82268	50	3779416	0	49	78126	81352	81592	70351	302	70797	80010	20	80000	20	160000	80084	80084	1	1	80021	10	9	10	80000	10	80000	10	80000	60	0	0	80000	5	0	0	80000	60	0	5020	0	2	16	5	2	2	80044	0	19	19	15	80000	10	80085	80085	80085	80085	80085

STLRH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations