Firestorm: LDURSB (64-bit) measurements

Code:

  ldursb x0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	1	1	1	0	48	0	2	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	39	73	1	16	1	1	396	9	9	2	1000	400	400	400	399	400
1004	399	3	1	1	0	1	1	1	41	1	2	379	2	12	12	16	25	1000	1000	1000	14989	0	394	389	212	3	252	1000	1000	1000	394	72	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	39	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	1	0	45	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	389	389	212	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	39	73	1	16	1	1	386	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	0	45	0	2	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	1	1	45	1	2	379	2	12	12	16	25	1000	1000	1000	15037	0	389	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	1	1	45	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	389	389	217	3	249	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	0	0	0	0	46	1	1	379	2	12	12	16	25	1000	1000	1000	15018	0	399	394	217	3	252	1000	1000	1000	394	72	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	386	10	10	2	1000	395	395	395	395	390
1004	389	3	0	0	0	0	1	1	45	1	1	374	2	18	18	12	25	1000	1000	1000	14838	0	394	394	217	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	39	73	1	16	1	1	391	10	6	4	1000	395	395	395	390	395
1004	394	2	0	0	0	0	1	1	45	0	2	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	43	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	395	390	390	390
1004	389	3	0	0	0	1	1	1	41	1	2	374	3	12	12	16	25	1000	1000	1000	15037	0	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	0	39	1039	6	1	35	43	73	1	16	1	1	386	10	10	4	1000	395	395	395	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursb x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	1	1	0	0	1	0	1	0	70020	69781	59748	25	40104	30103	10007	30403	10007	615567	3342615	0	49	66970	70035	70035	64699	6	64984	40118	30230	10010	60260	10010	70050	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	55	0	10000	1	0	1	1	1	1	2619	0	16	0	0	69855	30000	9	6	6	10000	30100	70036	70051	70051	70051	70105
40204	70072	524	0	0	0	0	1	0	1	0	70020	69786	59695	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66970	70035	70047	64643	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	12	10000	1	0	0	0	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70036	70051	70036	70051	70090
40204	70050	524	0	0	0	0	1	0	0	0	70035	69781	59695	25	40104	30100	10001	30100	10000	616005	3341470	0	49	66975	70050	70050	64646	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	50	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	9	0	9	10000	30100	70048	70051	70048	70051	70070
40204	70050	524	0	0	0	0	1	0	1	0	70020	69786	59709	25	40104	30103	10001	30100	10000	616005	3341470	0	49	66970	70035	70050	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	36	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	9	6	0	10000	30100	70036	70051	70048	70036	70101
40204	70050	525	0	0	0	0	0	0	1	0	70020	69786	59709	25	40100	30103	10001	30100	10000	616005	3341470	0	49	66967	70047	70047	64643	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	41	3	10000	1	0	0	0	0	0	2610	1	71	1	1	69813	30000	9	6	0	10000	30100	70036	70051	70051	70051	70101
40204	70035	525	0	0	0	0	1	0	0	0	70020	69764	59695	25	40104	30103	10001	30100	10000	616005	3341470	0	49	66970	70050	70050	64643	3	64938	40100	30200	10000	60200	10000	70050	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	2	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30000	9	0	0	10000	30100	70051	70036	70036	70036	70099
40204	70047	524	0	0	0	0	1	0	0	0	70020	69764	59709	25	40100	30103	10000	30100	10000	616005	3342062	0	49	66970	70050	70050	64646	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	37	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	9	9	0	10000	30100	70055	70051	70037	70051	70048
40204	70052	525	0	0	0	0	1	0	1	0	70020	69781	59695	25	40100	30103	10001	30100	10000	616005	3341470	0	49	66955	70050	70050	64631	3	64938	40310	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	27	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	0	0	9	10000	30100	70051	70051	70036	70036	70101
40204	70050	524	0	0	0	0	0	0	0	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616175	3342062	0	49	66970	70050	70050	64631	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	29	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69798	30003	0	6	9	10000	30100	70051	70051	70051	70051	70077
40204	70050	524	0	0	0	0	0	0	0	0	70035	69786	59709	25	40100	30103	10000	30100	10000	616609	3342110	0	49	66967	70050	70050	64646	3	64950	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	51	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69813	30003	9	6	0	10000	30100	70051	70051	70036	70051	70081

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70056	524	1	0	0	1	1	0	221	1	0	0	70041	69780	59715	25	40018	30016	10002	30010	10000	617036	3342494	0	49	66973	70056	70056	64671	3	64966	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	0	10001	0	1	0	1	10000	1	1	1	1	2	2520	0	1	71	1	1	69816	30003	9	6	0	10000	30010	70042	70057	70057	70054	70057
40025	70056	524	1	1	0	0	0	0	26	0	0	1	70041	69780	59701	25	40018	30016	10002	30010	10000	616995	3342494	0	49	66976	70041	70041	64659	3	64981	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	1	1	10000	1	1	0	1	1	2520	0	1	71	1	1	69818	30006	9	9	9	10000	30010	70057	70057	70057	70057	70057
40024	70056	524	1	0	1	0	0	0	44	0	0	1	70041	69780	59701	25	40014	30016	10002	30010	10000	616995	3342494	1	49	66976	70056	70056	64674	3	64981	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	0	0	1	10000	1	1	1	1	0	2520	0	1	71	1	1	69824	30006	0	6	9	10000	30010	70057	70057	70057	70042	70057
40024	70056	525	1	1	0	0	0	0	38	0	0	0	70026	69777	59701	25	40014	30016	10002	30010	10000	617036	3342494	0	49	66961	70061	70056	64758	3	64981	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	0	10001	0	1	1	4	10000	0	1	1	1	2	2520	0	1	71	1	2	69819	30006	6	9	0	10000	30010	70057	70054	70054	70054	70042
40024	70056	525	1	0	1	1	0	0	49	0	0	0	70041	69702	59701	25	40014	30016	10002	30010	10000	617036	3342494	0	49	66984	70056	70056	64671	3	64981	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	0	1	10000	1	1	1	1	1	2520	0	1	71	1	1	69819	30006	9	9	6	10000	30010	70057	70057	70057	70054	70054
40024	70056	525	1	1	1	1	0	0	38	0	0	0	70041	69780	59715	25	40018	30016	10002	30010	10000	617036	3342494	0	49	66976	70056	70041	64671	3	64966	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10001	0	0	1	1	10000	1	1	1	1	2	2520	0	1	71	1	1	69819	30003	9	6	0	10000	30010	70062	70058	70054	70057	70057
40024	70054	525	1	0	1	1	0	0	68	1	0	0	70038	69702	59701	25	40014	30016	10002	30010	10000	617009	3342350	0	49	66976	70056	70041	64671	3	64978	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	1	1	10000	1	1	1	1	1	2520	0	1	71	1	1	69804	30003	9	0	6	10000	30010	70054	70042	70158	70057	70057
40024	70041	525	1	1	0	1	0	0	59	1	0	1	70041	69702	59701	25	40018	30016	10001	30010	10000	617009	3342494	0	49	66961	70056	70041	64671	3	65036	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10002	0	0	1	1	10000	1	1	1	1	0	2520	0	2	71	1	1	69819	30006	0	9	9	10000	30010	70057	70042	70057	70042	70057
40024	70056	525	1	1	1	1	0	0	40	0	0	0	70041	69780	59701	25	40018	30016	10002	30010	10000	617036	3342494	1	49	66961	70056	70056	64671	24	64966	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10002	0	0	0	1	10000	1	1	1	1	0	2520	0	1	71	1	1	69819	30006	6	9	6	10000	30010	70057	70042	70058	70042	70057
40024	70056	524	1	1	0	1	0	0	35	1	0	0	70026	69702	59715	25	40018	30016	10002	30010	10000	616995	3342494	1	49	66976	70056	70041	64767	3	64966	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10003	0	1	0	4	10000	0	1	1	1	0	2520	0	2	71	1	1	69819	30003	0	6	9	10000	30010	70057	70057	70042	70057	70054

Test 3: throughput

Count: 8

Code:

  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]
  ldursb x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	1	0	0	0	1	0	0	26707	0	18	18	12	25	80100	100	80000	100	80000	500	1167808	49	23627	3	26828	26742	16659	3	16665	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	80000	0	35	80036	6	1	35	0	5110	1	16	1	1	26730	0	6	6	0	80000	100	26723	26708	26723	26708	26708
80204	26707	200	0	1	0	0	41	0	0	0	26707	2	18	12	12	25	80100	100	80000	100	80000	500	1166525	49	23642	0	26707	26722	16645	3	16680	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	1	35	80035	6	1	0	39	5111	1	16	1	1	26723	0	0	6	0	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	1	0	1	26707	2	0	12	12	25	80100	100	80000	100	80000	500	1166525	49	23627	0	26707	26722	16645	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	80035	0	35	80000	6	1	35	39	5110	1	16	2	3	26726	0	0	6	2	80000	100	26723	26723	26723	26723	26723
80204	26707	200	0	0	0	0	41	1	0	1	26707	2	0	18	12	49	80100	100	80000	100	80000	500	1167808	49	23627	0	26722	26707	16645	3	16665	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	35	80035	6	1	35	39	5110	1	16	2	1	26704	0	6	0	2	80000	100	26723	26723	26708	26708	26708
80204	26722	200	0	0	0	0	41	0	0	0	26707	2	18	18	0	25	80100	100	80000	100	80000	500	1166525	49	23627	0	26722	26707	16645	3	16680	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80035	0	35	80000	0	1	36	0	5110	2	16	1	1	26719	0	0	6	2	80000	100	26708	26723	26708	26723	26728
80204	26707	200	0	0	0	0	41	0	0	1	26707	2	0	18	0	25	80100	100	80000	100	80000	500	1166525	49	23642	0	26707	26722	16630	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	0	80035	6	0	0	43	5111	1	16	1	1	26723	0	6	6	2	80000	100	26723	26708	26723	26723	26723
80204	26707	200	0	0	0	0	41	1	0	1	26707	0	18	0	12	25	80100	100	80000	100	80000	500	1166525	49	23642	0	26707	26707	16645	14	16680	80100	200	80000	200	80000	26876	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	0	80000	0	0	0	0	5110	1	16	1	1	26732	0	6	6	0	80000	100	26708	26708	26723	26723	26723
80204	26722	200	0	0	0	0	41	1	0	0	26707	2	0	18	0	25	80100	100	80000	100	80000	500	1166818	49	23642	0	26707	26707	16645	3	16665	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	0	80035	6	1	0	0	5110	1	16	3	1	26781	0	6	6	0	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	0	0	0	26707	2	0	0	12	25	80100	100	80000	100	80000	500	1167808	49	23647	0	26722	26722	16630	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	0	80035	6	1	35	39	5110	1	16	1	1	26719	0	6	6	2	80000	100	26723	26723	26723	26708	26723
80204	26707	200	0	1	1	0	0	1	0	1	26692	2	18	0	12	25	80100	100	80000	100	80000	500	1166525	49	23627	0	26722	26722	16630	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	39	80000	6	1	0	0	5110	1	16	1	1	26719	0	6	0	0	80000	100	26723	26708	26708	26723	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	1	59	1	0	26886	0	12	12	19	25	80010	10	80000	10	80000	50	1166750	1	1	49	23651	26708	26799	16891	3	16718	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80039	0	38	80038	6	1	0	0	0	5020	13	16	17	13	26725	10	10	4	80000	10	26709	26729	26728	26728	26728
80024	26728	200	0	0	59	0	1	26712	2	0	12	19	25	80010	10	80000	10	80000	50	1167124	0	1	49	23628	26732	26727	16672	3	16713	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80038	6	0	0	0	0	5020	13	16	19	15	26728	14	14	7	80000	10	26729	26709	26732	26709	26732
80024	26727	200	0	0	15	1	1	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1166896	0	0	49	23651	26708	26727	16693	3	16813	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	0	80038	0	1	39	43	0	5020	11	16	12	16	26728	0	14	7	80000	10	26732	26709	26728	26728	26709
80024	26731	200	0	0	269	1	1	26859	0	12	12	0	25	80010	10	80000	10	80000	50	1166750	0	1	49	23647	26731	26731	16672	3	16713	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	43	80038	6	1	0	43	0	5020	17	16	12	13	26766	14	14	7	80000	10	26728	26732	26729	26729	26709
80024	26708	201	0	0	47	0	0	26716	0	1	0	19	25	80010	10	80000	10	80000	50	1168843	0	1	49	23648	26708	26708	16672	3	16695	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80038	0	0	80038	6	1	38	43	0	5020	11	16	13	10	26728	14	0	7	80000	10	26709	26709	26709	26732	26709
80024	26731	200	0	0	59	0	0	26780	2	12	12	21	25	80010	10	80000	10	80000	50	1167201	0	1	49	23651	26731	26731	16672	3	16719	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80038	6	1	39	0	0	5020	13	16	14	14	26725	14	14	0	80000	10	26729	26732	26732	26732	26732
80024	26727	200	1	1	33	1	1	26713	2	0	1	0	25	80010	10	80000	10	80000	50	1167124	0	1	49	23628	26708	26731	16672	3	16695	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	39	80039	6	1	39	0	0	5020	16	16	14	16	26705	10	10	4	80000	10	26728	26709	26728	26709	26729
80024	26731	201	0	0	60	0	1	26693	0	1	1	19	25	80010	10	80000	10	80198	50	1167201	1	1	49	23651	26731	26708	16672	3	16716	80010	20	80000	20	80000	26731	80	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	38	80000	6	1	39	44	0	5020	12	16	13	16	26725	0	0	7	80000	10	26729	26729	26732	26728	26709
80024	26731	200	0	0	0	0	1	26716	2	1	1	16	25	80010	10	80000	10	80000	50	1167201	0	1	49	23651	26728	26708	16672	3	16707	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	38	80038	6	1	39	44	0	5020	16	16	12	16	26724	10	10	0	80000	10	26709	26732	26732	26728	26709
80024	26728	200	0	0	24	1	1	26693	2	1	0	0	25	80010	10	80000	10	80000	50	1167124	0	1	49	23647	26727	26708	16672	3	16715	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	80040	0	0	39	0	0	5020	18	16	14	17	26705	7	10	7	80000	10	26709	26728	26709	26729	26728

LDURSB (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations