Firestorm: LDR (pre-index, 64-bit) measurements

Code:

  ldr x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1047	8	0	0	0	0	140	19	0	0	2	0	1032	0	93	0	2	26	25	2000	1000	1000	1000	1000	52828	45833	1	1047	1048	699	3	778	2000	1000	1000	1000	1000	1047	44	1	1	1001	1000	1000	0	1028	7	1	55	1140	1	1	15	6	114	1130	43	9	98	55	7	1	0	73	2	16	2	2	1041	1000	43	32	1000	1000	1048	1048	1049	1048	1047
2004	1047	8	1	1	0	0	168	14	1	0	1	0	1033	8	92	1	1	24	25	2000	1000	1000	1000	1000	52816	45844	1	1048	1063	701	3	781	2000	1000	1000	1000	1000	1048	44	1	1	1001	1000	1000	0	1023	0	1	50	1133	6	0	17	12	106	1119	36	6	105	50	0	0	0	73	2	16	2	2	1041	1000	31	43	1000	1000	1050	1065	1049	1047	1048
2004	1059	8	1	0	1	0	192	12	1	0	0	0	1031	21	101	2	8	26	25	2000	1000	1000	1000	1000	52816	45844	1	1048	1047	699	3	781	2000	1000	1000	1000	1000	1047	44	1	1	1001	1000	1000	0	1034	0	0	63	1117	3	1	20	8	107	1126	35	4	103	39	0	0	0	73	2	16	2	2	1041	1000	30	26	1000	1000	1047	1066	1048	1048	1048
2004	1048	7	0	0	0	0	144	22	1	0	6	0	1032	16	95	5	9	24	25	2000	1000	1000	1000	1000	52824	45834	1	1047	1048	701	3	784	2000	1000	1000	1000	1000	1048	44	1	1	1001	1000	1000	0	1025	0	0	40	1137	6	0	24	12	103	1126	29	6	112	63	0	0	0	73	2	16	2	2	1040	1000	33	32	1000	1000	1049	1047	1049	1048	1049
2004	1048	7	1	1	1	0	155	23	1	0	4	0	1050	6	96	4	3	27	25	2000	1000	1000	1000	1000	52824	45840	1	1058	1060	699	3	781	2000	1000	1000	1000	1000	1048	44	1	1	1001	1000	1000	0	1029	8	0	41	1144	4	0	21	0	109	1116	35	7	106	55	7	2	0	73	2	16	2	2	1041	1000	48	35	1000	1000	1049	1049	1048	1049	1049
2004	1048	7	0	0	0	1	139	23	0	0	5	20	1034	13	93	3	2	25	25	2000	1000	1000	1000	1000	52804	45848	1	1048	1047	699	3	782	2000	1000	1000	1000	1000	1046	44	1	1	1001	1000	1000	2	1020	0	0	63	1126	0	1	18	14	118	1121	18	3	107	63	7	0	0	73	2	16	2	2	1034	1000	31	30	1000	1000	1048	1047	1049	1048	1049
2004	1047	8	0	0	0	0	178	22	0	0	7	0	1032	0	95	5	9	29	25	2000	1000	1000	1000	1000	52816	45841	1	1048	1046	701	3	780	2000	1000	1000	1000	1000	1046	44	1	1	1001	1000	1000	0	1000	0	0	49	1104	0	0	0	0	107	1124	36	6	106	47	0	0	0	73	2	16	2	2	1025	1000	35	28	1000	1000	1050	1047	1049	1049	1047
2004	1046	8	0	0	0	0	160	22	0	0	6	4	1032	9	94	3	3	28	25	2000	1000	1000	1000	1000	52828	45836	1	1048	1065	699	3	780	2000	1000	1000	1000	1000	1047	44	1	1	1001	1000	1000	0	1030	8	0	46	1120	2	0	13	0	110	1119	24	4	108	63	6	1	0	73	2	16	2	2	1039	1000	33	36	1000	1000	1049	1050	1047	1065	1048
2004	1047	8	0	0	0	0	127	0	0	0	7	0	1033	9	93	3	2	27	25	2000	1000	1000	1000	1000	52820	45838	1	1048	1049	699	3	782	2000	1000	1000	1000	1000	1047	44	1	1	1001	1000	1000	0	1018	0	0	48	1121	0	1	23	16	132	1118	41	4	101	47	7	0	0	73	2	16	2	2	1039	1000	31	33	1000	1000	1048	1049	1048	1048	1048
2004	1047	8	1	1	0	0	173	0	0	0	9	0	1031	10	90	7	6	22	25	2000	1000	1000	1000	1000	52836	45840	1	1048	1047	701	3	781	2000	1000	1000	1000	1000	1047	44	1	1	1001	1000	1000	0	1012	6	0	55	1118	2	0	17	6	107	1116	36	4	101	31	0	0	0	73	2	16	2	2	1041	1000	27	21	1000	1000	1049	1049	1048	1047	1048

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1854

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	71998	538	0	0	0	0	0	0	0	0	584	841	1	632	3	164	71843	792	5	4	71579	25	50770	40636	10132	40100	10000	614801	2728097	1	49	68553	0	71822	71843	65349	7	3	65456	50100	40200	10000	70200	10000	71830	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10929	0	156	509	10666	288	11	919	42	23	10908	136	9	137	1	0	3	2610	2	51	1	1	71667	40536	1004	944	912	10000	40100	71991	71848	71832	71728	71839
50204	71921	559	1	0	0	0	0	0	0	0	583	847	1	720	3	108	71620	830	6	0	71662	25	50785	40640	10143	40100	10000	614734	2727441	1	49	68696	0	71794	71698	65215	0	3	65548	50100	40200	10000	70200	10000	71889	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10915	1	148	534	10675	289	13	926	42	24	10943	137	4	123	1	0	3	2610	1	56	1	1	71665	40516	878	902	915	10000	40100	71901	71730	71906	71829	71795
50204	71880	537	0	0	0	0	0	0	0	0	542	846	1	696	2	296	71716	826	4	0	71387	25	50690	40652	10119	40100	10000	677052	2725205	1	49	68584	0	71755	71689	65138	0	3	65575	50100	40200	10000	70200	10000	71788	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10907	11	145	510	10647	274	12	944	66	45	10974	141	10	125	1	0	10	2610	1	51	1	2	71642	40508	882	890	933	10000	40100	71823	71752	72006	71866	71853
50204	71900	536	1	0	0	0	0	0	0	0	610	835	1	704	1	104	71799	818	3	0	71434	25	50675	40644	10141	40100	10000	676916	2719271	1	49	68634	0	71790	71952	65275	0	3	65553	50100	40200	10000	70200	10000	71844	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10878	9	166	539	10630	287	11	913	28	40	10917	122	6	137	2	0	5	2610	1	58	1	1	71552	40560	1040	952	948	10000	40100	71824	71811	71857	71882	71704
50204	71865	539	1	0	0	0	0	0	0	0	533	817	1	720	2	176	71746	829	7	1	71595	25	50755	40648	10131	40100	10000	675015	2717748	1	49	68683	0	71696	71940	65232	0	3	65366	50100	40200	10000	70200	10000	71748	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10930	1	149	503	10647	292	13	904	40	39	10921	129	6	122	1	3	12	2610	1	51	1	1	71770	40560	896	966	935	10000	40100	71488	71920	71895	71997	71960
50204	71737	537	0	0	0	0	0	0	0	0	578	866	1	728	0	248	71784	802	4	0	71671	25	50810	40692	10148	40100	10000	677882	2716692	0	49	68702	0	71900	71831	65179	0	3	65576	50100	40200	10000	70200	10000	71592	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10978	1	164	472	10687	291	11	880	48	34	10927	130	9	126	1	0	6	2610	1	51	1	1	71662	40556	924	948	924	10000	40100	71829	71789	71811	71830	71894
50204	71901	537	2	0	0	0	0	0	0	0	578	903	1	672	2	156	72099	792	4	4	71652	25	50785	40676	10140	40100	10000	680108	2726038	0	49	68663	0	71874	71775	65270	7	3	65608	50100	40200	10000	70200	10000	71852	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10972	0	151	483	10680	282	9	945	54	37	10975	124	4	131	0	3	3	2610	1	51	1	1	71778	40576	922	926	989	10000	40100	71861	71885	71873	71757	71776
50204	71780	539	1	0	0	0	1	0	0	0	541	850	1	720	1	140	71849	801	3	8	71558	25	50745	40644	10136	40100	10000	678086	2710212	0	49	68853	0	71771	71876	65181	0	3	65602	50100	40200	10000	70200	10000	71720	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10940	0	179	488	10661	273	13	952	68	34	10947	135	6	135	0	0	3	2610	1	51	1	1	71586	40580	970	906	1029	10000	40100	71921	71997	71996	71940	72017
50204	71777	538	0	0	0	0	0	0	0	0	628	812	1	704	1	96	71851	833	3	4	71512	25	50760	40648	10140	40100	10000	678269	2720689	1	49	68506	0	71761	71643	65370	0	3	65451	50100	40200	10000	70200	10000	71660	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10907	4	142	503	10669	271	21	898	32	39	10927	122	10	129	2	3	9	2610	1	58	1	1	71627	40548	856	816	1030	10000	40100	71452	71878	71867	71787	71938
50204	71771	539	2	2	0	2	0	0	0	0	543	809	1	728	1	288	71640	781	2	0	71643	25	50765	40616	10130	40100	10000	678711	2724741	1	49	68870	0	71802	72018	65400	0	3	65592	50100	40200	10000	70566	10000	71795	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10946	13	164	550	10650	275	14	876	98	41	10953	132	8	122	2	2	7	2610	1	51	1	1	71669	40588	1014	990	967	10000	40100	71936	71912	71776	71744	71965

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1830

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72224	539	1	3	0	1	0	0	0	513	0	860	1	720	3	112	71823	814	6	5	71447	25	50680	40554	10135	40010	10000	614308	2730294	0	0	49	68951	71755	71739	65265	0	3	65675	50010	40020	10000	70020	10000	71845	35	1	1	40021	10	9	10	10000	30010	10000	0	10	11013	1	139	518	10654	266	10	911	86	40	10938	130	8	131	1	3	7	0	0	2520	0	11	85	0	7	11	71767	40588	968	1022	902	10000	40010	71910	71751	71808	71836	71759
50024	71688	538	0	1	0	0	0	0	0	537	0	827	2	736	1	120	71740	795	7	3	71648	25	50690	40546	10145	40010	10000	613289	2727363	0	0	49	68763	71907	71686	65186	0	3	65599	50010	40020	10000	70020	10000	72079	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10924	1	149	514	10659	258	11	952	80	42	10943	138	8	124	1	0	6	0	0	2520	0	7	85	0	10	7	71919	40592	910	854	942	10000	40010	71977	72012	71726	71836	71829
50024	71912	538	0	1	0	0	0	0	0	511	0	845	1	720	1	104	71849	800	5	4	71733	25	50785	40574	10124	40010	10000	614094	2724245	0	0	49	66323	71874	71901	65228	0	3	65502	50010	40020	10000	70020	10000	71820	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10901	1	143	508	10665	263	13	920	78	29	10976	135	6	130	1	0	5	0	0	2520	0	8	85	0	8	12	71588	40576	916	880	998	10000	40010	71897	71787	71795	71895	71858
50024	71869	538	0	1	0	1	0	0	0	578	0	883	1	520	2	112	71714	812	6	0	71635	25	50735	40566	10138	40010	10000	611336	2726554	0	1	49	68722	71770	71865	65206	0	3	65479	50010	40020	10000	70020	10000	71889	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10915	1	150	506	10646	257	8	936	82	37	10969	134	6	146	1	0	3	0	0	2520	0	7	85	0	7	8	71688	40568	1028	996	966	10000	40010	71727	71886	71995	71747	72092
50024	71786	538	0	1	0	0	0	0	0	485	0	828	2	712	2	108	71658	818	7	3	71755	25	50660	40562	10144	40010	10000	612500	2728535	0	1	49	68807	71850	71867	65237	0	3	65529	50010	40020	10000	70020	10000	71547	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10911	1	140	522	10664	261	10	926	80	28	10971	142	7	121	1	0	4	0	0	2520	0	7	85	0	7	11	71715	40568	998	958	902	10000	40010	71850	71896	71897	71902	71730
50024	71888	538	0	1	1	0	0	0	0	574	0	836	1	736	2	160	71789	829	4	4	71686	25	50655	40550	10138	40010	10000	611252	2729875	0	1	49	68850	71733	71735	65358	0	3	65572	50010	40020	10000	70020	10000	71910	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10899	1	145	522	10620	293	14	912	40	47	10957	126	13	142	1	0	2	0	0	2520	0	6	85	0	7	12	71500	40516	1070	978	918	10000	40010	71966	71802	71956	71695	72070
50024	71801	538	0	1	0	0	0	0	0	474	0	853	1	712	2	116	71701	822	6	1	71557	25	50735	40590	10133	40010	10000	613358	2727775	0	0	49	68840	71684	71839	65225	0	3	65411	50010	40020	10000	70020	10000	71907	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10897	2	149	513	10641	261	16	912	54	47	10949	135	11	129	1	2	3	0	0	2520	0	5	71	0	6	10	71743	40524	984	1008	976	10000	40010	71651	71890	71903	71872	71901
50024	71916	537	0	1	0	0	0	0	0	532	0	824	1	712	2	112	71845	790	5	5	71581	25	50655	40634	10129	40010	10000	613712	2718582	0	0	49	68748	71718	71783	65499	0	3	65391	50570	40183	10083	70020	10000	71830	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10900	1	149	521	10666	262	9	914	52	39	10969	129	7	127	1	30	6	0	0	2520	0	6	85	0	10	8	71486	40620	930	936	992	10000	40010	71859	72029	71897	71923	71739
50024	71708	537	0	1	0	1	0	0	0	510	0	825	1	608	3	112	71815	816	10	2	71742	25	50715	40630	10144	40010	10000	611642	2724312	0	0	49	68635	71773	71865	65208	0	3	65492	50010	40020	10000	70020	10000	72044	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10909	1	146	513	10642	254	13	906	80	44	10937	134	8	133	1	0	3	0	0	2520	0	7	85	0	6	7	71621	40536	854	1078	958	10000	40010	71858	71839	71759	71809	71861
50024	71866	539	0	1	0	0	0	0	0	586	0	832	1	728	2	116	71537	831	6	3	71595	25	50655	40526	10140	40010	10000	610417	2723644	0	0	49	68571	71645	71916	65249	0	3	65501	50010	40020	10000	70020	10000	71847	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10897	1	160	496	10633	249	10	917	42	37	10956	107	7	112	1	0	5	0	0	2520	0	6	85	0	10	7	71649	40544	962	962	852	10000	40010	71872	71937	72022	71976	71918

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6, #8]!
  ldr x0, [x7, #8]!
  ldr x0, [x8, #8]!
  ldr x0, [x9, #8]!
  ldr x0, [x10, #8]!
  ldr x0, [x11, #8]!
  ldr x0, [x12, #8]!
  ldr x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29562	220	2	2	0	0	0	7158	809	1	704	106	148	29379	822	340	1753	1823	2050	25	160150	80164	80000	80100	80000	400759	1292965	1	64	49	26179	29322	29316	9329	0	3	9331	160100	80200	80000	80200	80000	29358	35	1	1	80201	100	99	46	100	80000	100	80000	100	80981	37	411	5633	85223	689	11	989	46	5069	86221	709	124	4876	5732	36	5	4	5110	1	17	1	1	29286	24	80064	568	555	93	80000	80100	29390	29278	29272	29371	29349
160204	29410	220	3	0	0	0	0	6700	828	1	736	113	144	29476	805	357	1782	1748	1986	25	160152	80155	80000	80100	80000	400814	1289098	0	50	49	26137	29437	29480	9413	0	3	9527	160100	80200	80000	80200	80000	29364	35	1	1	80201	100	99	48	100	80000	100	80000	100	80986	56	399	5299	85423	662	13	984	42	5153	85783	767	129	4894	5031	55	0	3	5110	1	16	1	1	29498	29	80055	514	540	92	80000	80100	29297	29209	29351	29401	29350
160204	29456	220	2	1	1	0	0	6948	835	1	736	116	144	29329	804	323	1573	1647	2146	25	160153	80148	80000	80100	80000	400766	1297490	0	68	49	26279	29341	29431	9393	0	3	9415	160100	80200	80000	80200	80000	29267	35	1	1	80201	100	99	50	100	80000	100	80000	100	80967	51	400	5651	84736	692	12	966	66	4669	86059	744	129	5222	5540	53	0	3	5110	1	16	1	1	29358	46	80069	569	532	106	80000	80100	29539	29272	29448	29086	29299
160204	29488	222	2	0	0	0	0	7147	843	1	720	125	128	29378	846	413	1791	1717	2004	25	160142	80156	80000	80100	80000	400792	1296049	0	39	49	26323	29438	29246	9234	0	3	9277	160100	80200	80000	80200	80000	29315	35	1	1	80201	100	99	36	100	80000	100	80000	100	80958	37	382	5304	85529	702	9	968	48	4913	86233	701	127	4657	5002	19	0	5	5110	1	17	1	1	29294	25	80055	617	553	93	80000	80100	29274	29374	29230	29264	29553
160204	29448	220	1	0	0	0	0	6641	831	1	720	146	264	29345	807	375	1832	1871	2012	25	160148	80154	80000	80100	80000	400772	1299186	0	67	49	26268	29297	29264	9293	0	3	9598	160100	80200	80000	80200	80000	29559	35	1	1	80201	100	99	59	100	80000	100	80000	100	80938	19	433	5112	85220	706	15	989	54	4425	85681	793	128	4679	5591	19	0	4	5110	1	16	1	1	29213	34	80055	609	513	98	80000	80100	29575	29383	29359	29263	29457
160204	29378	220	2	0	0	0	0	6732	851	1	720	131	108	29523	815	332	1712	1682	2256	25	160172	80171	80000	80100	80000	400767	1296434	0	57	49	26153	29400	29280	9198	0	3	9230	160100	80200	80000	80200	80000	29233	35	1	1	80201	100	99	54	100	80000	100	80000	100	80978	40	388	5538	85109	686	9	942	34	4530	85743	815	132	4891	5820	36	0	5	5110	1	17	1	1	29490	35	80056	643	541	100	80000	80100	29394	29455	29402	29520	29334
160204	29452	222	2	0	0	0	0	6366	845	1	632	118	92	29250	811	354	1561	2008	2007	25	160141	80175	80000	80100	80000	400779	1300129	0	61	49	26557	29406	29520	9200	0	3	9359	160100	80200	80000	80200	80000	29370	35	1	1	80201	100	99	59	100	80000	100	80000	100	80974	35	400	5892	85401	691	9	976	54	5149	85562	752	115	5244	5261	19	0	2	5110	1	16	1	1	29366	35	80056	558	595	105	80000	80100	29647	29300	29382	29371	29350
160204	29410	222	1	0	0	0	0	6633	834	1	712	141	108	29391	801	338	1545	1577	2047	25	160161	80160	80000	80100	80000	400778	1317342	1	67	49	26337	29264	29478	9412	0	3	9415	160100	80200	80000	80200	80000	29405	35	1	1	80201	100	99	45	100	80000	100	80000	100	80945	19	372	5200	84823	727	10	973	72	4976	86163	813	121	5293	5116	19	0	7	5110	1	16	1	1	29410	31	80050	570	579	108	80000	80100	29388	29282	29196	29332	29299
160204	29307	220	1	0	0	0	1	6455	822	1	720	118	148	29436	913	361	1684	1777	2050	25	160143	80174	80000	80100	80000	400734	1295143	0	63	49	26153	29394	29335	9191	0	3	9393	160100	80200	80000	80200	80000	29431	35	1	1	80201	100	99	38	100	80000	100	80000	100	80981	37	390	5700	84774	673	10	974	50	4788	85719	825	136	4794	5457	36	3	3	5110	1	17	1	1	29560	31	80063	517	554	103	80000	80100	29238	29355	29359	29262	29457
160204	29318	221	2	0	0	0	0	6708	826	1	736	109	68	29197	809	334	1689	1687	2048	25	160151	80151	80000	80100	80000	400769	1301195	0	54	49	26326	29259	29195	9232	0	3	9616	160100	80200	80000	80200	80000	29572	35	1	1	80201	100	99	54	100	80000	100	80000	100	80967	19	409	5285	85468	657	13	996	88	5043	86248	716	132	5214	5719	19	0	3	5110	1	16	1	1	29296	32	80062	623	578	97	80000	80100	29472	29519	29459	29506	29441

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3677

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29710	220	1	0	0	0	1	6570	832	1	728	109	128	29377	813	355	1798	1790	2387	25	160070	80070	80000	80010	80000	400383	1311935	0	51	49	26310	29369	29470	9227	3	9234	160010	80020	80000	80020	80000	29207	35	1	1	80021	10	9	43	10	80000	10	80000	0	10	80900	0	417	5440	85289	665	11	912	76	5203	85650	811	118	4604	4647	18	3	0	5020	6	16	0	6	7	29403	40	80074	523	553	88	80000	80010	29503	29478	29377	29417	29436
160024	29574	220	1	0	0	0	0	7201	809	1	728	120	164	29479	788	378	1728	1685	2158	25	160072	80061	80000	80010	80000	400311	1316913	0	57	49	26263	29465	29567	9196	3	9293	160010	80020	80000	80020	80000	29614	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80929	18	407	5515	85209	671	11	919	78	4861	86601	814	140	4998	5239	0	0	3	5020	6	16	0	4	6	29520	36	80053	617	610	83	80000	80010	29407	29370	29358	29434	29338
160024	29169	219	1	0	1	0	0	6801	833	1	728	114	108	29342	797	363	1883	1577	2219	25	160061	80070	80000	80010	80000	400302	1315125	0	56	49	26041	29278	29188	9169	3	9418	160010	80020	80000	80020	80000	29180	35	1	1	80021	10	9	42	10	80000	10	80000	0	10	80918	0	398	5960	85062	637	9	948	136	4994	86648	818	139	5198	4930	17	3	3	5020	4	16	0	4	3	29451	36	80052	628	558	101	80000	80010	29443	29464	29566	29405	29374
160024	29408	221	1	0	0	0	0	6561	814	1	720	127	100	29201	829	368	1747	1864	2223	25	160063	80071	80000	80010	80000	400362	1316115	0	60	49	26319	29553	29409	9454	3	9399	160010	80020	80000	80020	80000	29251	35	1	1	80021	10	9	39	10	80000	10	80000	0	10	80934	16	394	5968	85396	727	10	928	50	4862	86254	874	134	4718	5806	0	0	3	5020	4	16	0	5	3	29550	33	80052	607	612	115	80000	80010	29337	29580	29594	29466	29585
160024	29358	220	1	0	0	0	0	6867	831	1	736	115	156	29256	825	405	1670	1834	2087	25	160062	80079	80000	80010	80000	400354	1303187	0	63	49	26265	29291	29385	9369	3	9380	160010	80020	80000	80020	80000	29394	35	1	1	80021	10	9	33	10	80000	10	80000	0	10	80932	0	389	5600	85192	665	11	925	78	5113	85991	758	138	4538	5106	0	0	3	5020	3	16	0	4	3	29331	37	80058	584	500	92	80000	80010	29324	29353	29456	29506	29509
160024	29264	221	0	0	0	0	0	6275	829	1	728	101	112	29441	894	372	1643	1819	2174	25	160062	80070	80000	80010	80000	400330	1303454	0	56	49	26385	29288	29478	9318	3	9383	160010	80020	80000	80020	80000	29443	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80926	0	400	5097	85275	662	9	950	78	5047	86026	758	126	5023	4614	0	3	6	5020	4	16	0	3	4	29297	41	80057	521	571	102	80000	80010	29431	29300	29775	29430	29216
160024	29047	222	0	0	0	0	0	6781	825	1	712	118	192	29356	864	365	1569	1715	2341	25	160076	80075	80000	80010	80000	403632	1293681	0	51	49	26270	29298	29295	9126	3	9371	160010	80020	80000	80020	80000	29360	35	1	1	80021	10	9	41	10	80000	10	80000	0	10	80918	0	405	5436	85365	687	8	920	46	5440	86036	787	132	4929	4837	0	0	4	5020	4	16	0	3	4	29343	30	80071	601	580	100	80000	80010	29311	29268	29348	29430	29491
160024	29439	221	0	0	0	1	0	7002	837	1	728	120	108	29476	822	379	1759	1835	2125	25	160084	80073	80000	80010	80000	400333	1297859	0	67	49	26552	29426	29351	9377	3	9468	160010	80020	80000	80020	80000	29421	35	1	1	80021	10	9	37	10	80000	10	80000	0	10	80946	17	367	5775	85603	674	12	931	74	5095	86006	809	136	4667	5528	0	0	3	5020	4	16	0	4	3	29382	32	80070	626	540	99	80000	80010	29315	29280	29438	29379	29401
160024	29452	221	1	0	0	0	0	7049	850	1	744	105	96	29314	795	397	1632	1729	1965	25	160060	80072	80000	80010	80000	400329	1297466	0	52	49	26398	29316	29249	9284	3	9300	160010	80020	80000	80020	80000	29326	35	1	1	80021	10	9	40	10	80000	10	80000	0	10	80934	0	430	5056	85141	668	11	920	50	5395	86186	783	124	4821	4806	18	0	1	5020	4	16	0	4	4	29447	42	80067	671	610	112	80000	80010	29414	29431	29425	29429	29433
160024	29236	220	0	0	0	0	0	7168	860	1	744	122	132	29298	807	381	1751	1699	2205	25	160061	80061	80000	80010	80000	400309	1300758	0	63	49	26438	29350	29578	9359	3	9324	160010	80020	80000	80020	80000	29448	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80912	0	367	5468	85226	668	9	923	54	5528	85981	811	133	4843	5699	0	3	3	5020	3	16	0	6	6	29575	39	80069	577	578	107	80000	80010	29436	29553	29594	29498	29536

LDR (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations