Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AND (immediate, 64-bit)

Test 1: uops

Code:

  and x0, x0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110003073141119371000100010361036103610361036
10041035706186225100010001000169161103510357283868100010001000103541111001100002773141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110008073141119371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103589618622510001000100016916110351035728386810001176117110354111100110001073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  and x0, x0, #3
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575061987725101001010010100886641496955100351003585803872210100102001020010035411110201100991001010010001071033722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010001071023722994110000101001003610036100361003610036
1020410035750619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100002171023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010001071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
1020410035750619877251010010100101008866404969551003510035858038722102801020010200100354111102011009910010100100033371023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575061986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064034122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035751561986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
10024100357606198632510010100101001088784496955100351003586023874010010100201002010035411110021109101001010011464024122994010000100101003610036100361003610036
100241003576061986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575961986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750441986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575061986325100101001010010887844969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  and x0, x8, #3
  and x1, x8, #3
  and x2, x8, #3
  and x3, x8, #3
  and x4, x8, #3
  and x5, x8, #3
  and x6, x8, #3
  and x7, x8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413413100002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001621115119016001338780036801001339113391133911339113391
80204133901000028278013680136801484007101491031013390133903326633368014880264802641339039118020110099100801001000001115119016001338780036801001339113391133911339113391
8020413390100002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100081351115119016001338780036801001339113391133911339113391
80204133901000028278013680136801484007101491031013390133903326633368014880264802641339039118020110099100801001000001115119016001338780036801001339113391133911339113391
802041339010000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010010541115119016001338780036801001339113391133911339113391
802041339010000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010001401115119016001338780036801001339113391133911339113391
80204133901000028278013680136801484007101491031013390133903326633368014880264802641339039118020110099100801001000001115119016001338780036801001339113391133911339113391
8020413390100001322780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010005731115119016001338780036801001339113391133911339113391
802041339010000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000451115119016001338780036801001339113391133911339113391
802041339010000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010002201115119016001338780036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
8002413387100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101013050215195713368800000800101337213372133801337213372
8002413371100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050217197513368800000800101337213372133791337213372
8002413371100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050217197513368800000800101337213372133781337213372
800241337110000352580010800108001040005049102911337113371333033348800108002080020133713911800211091080010100108050215197513368800000800101337213372133791337213372
800241337110008835258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010110050215195713368800000800101337213372133781337213372
8002413371100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050215195713368800000800101337213372133801337213372
8002413371100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050217195713368800000800101337213372133791337213372
8002413371100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050215195713368800000800101337213372133811337213372
8002413371100003525800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050215197513368800000800101337213372133781337213372
8002413371100008425800108001080010400050491029113371133713330333488001080020800201337139118002110910800101000050217197513368800000800101337213372133781337213372